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| 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 features ? transceiver compliant with psi5 standard v1.3 and v2.1 ? provides four independent master channels (up to 6 sensors each) ? supporting 125 kbit/s and 189 kbit/s protocols ? supporting synchronous and asynchronous opera- tion modes ? various diagnostic features ? internal sync-voltage generation ? programmable psi5 channel-voltage 4.6v to 11v ? automatic threshold adaption to sensor quiescent current ? reverse polarity protected bus outputs up to 40v ? enables operation in powertrain and chassis control systems ? developed according to iso 26262, based on safety requirements rated up to asil c. ? operating temperature range -40c to +125c applications ? safety (airbag) control systems ? powertrain control systems ? vehicle dynamics control system general description the e521.41 was developed to manage the connection and communication between a microcontroller unit an d up to 24 sensor satellites. data transmission from the sensor to ecu is done by current modulation on the power supply lines with d ata rate of 125 kbit/s or 189 kbit/s (manchester coded) . data transmission from ecu to sensor is done by voltage modulation on the power supply. it supports bid- irectional communication. two methods are supported : ? tooth gap method ? pulse width method the device is a psi5 v1.3 and v2.1 compliant trans- ceiver which provides four independently operating channels. the channels are able to communicate in l ow power-, standard-, synchronous- and asynchronous operating mode. the communication to c is done via the spi o r uart interface. ordering information ordering-no.: features package E52141A62CXX2 4-channel qfn20l5 e52141a55e 4-channel soic20 typical application circuit elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.0 6 1 / 89
4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 functional diagram e521.41 csync cp2 cp1 vbus receiver threshold adaption timeslot control status register manchester decoder data register sync control oscillator 4 ua rt / spi interface cfg register bus enable error detection sync ctrl current limitation active discharge vsync charge pump vdd_int bandgap references vsupply vg vbus ldo control ncs sdo / rxd sdi /txd sclk nres trig vdd 4 4 sif1 sif2 sif3 sif4 + reverse prot + reverse prot elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 2 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 1 package pinout qfn20l5,so20 elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 3 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 1.1 pin description qfn20l5 table 1.1-1: pin description no name type description 1 dgnd s digital voltage supply 2 vdd s digital voltage supply 3 agnd s analog ground 4 sif1 hv_a_o sensor interface 1 5 sif3 hv_a_o sensor interface 3 6 pgnd s power ground 7 cp2 hv_a_o sync charge pump fly capacitor 8 vbus hv_s vbus voltage 9 cp1 hv_a_o sync charge pump fly capacitor 10 csync hv_s sync supply voltage 11 sif4 hv_a_o sensor interface 4 12 sif2 hv_a_o sensor interface 2 13 vg hv_a_o gate voltage for external transistor 14 vsuppply hv_s supply voltage 15 nres d_i negative reset and test mode pin 16 trig d_i sync pulse trigger input 17 ncs d_i spi chip select 18 sdi_rxd d_i spi or uart data input 19 sdo_txd d_o spi or uart data output 20 sclk d_i spi clock input ep s qfn20l5 package only exposed pad. connect to large copper ground plane f or optimal heat dissipation. connect to gnda and gndd. note: a = analog, d = digital, s = supply, i = input, o = output, b = bidirectional, hv = high voltage elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 4 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 1.2 pin description so20 table 1.2-1: pin description no name type description 1 sdo_txd d_o spi or uart data output 2 sclk d_i spi clock input 3 dgnd s digital ground 4 vdd s digital voltage supply 5 agnd s analog ground 6 sif1 hv_a_o sensor interface 1 7 sif3 hv_a_o sensor interface 3 8 pgnd s power ground 9 cp2 hv_a_o sync charge pump fly capacitor 10 vbus hv_s vbus voltage 11 cp1 hv_a_o sync charge pump fly capacitor 12 csync hv_s sync supply voltage 13 sif4 hv_a_o sensor interface 4 14 sif2 hv_a_o sensor interface 2 15 vg hv_a_o gate voltage for external transistor 16 vsuppply hv_s supply voltage 17 nres d_i negative reset and test mode pin 18 trig d_i sync pulse trigger input 19 ncs d_i spi chip select 20 sdi_rxd d_i spi or uart data input note: a = analog, d = digital, s = supply, i = input, o = output, b = bidirectional, hv = high voltage elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 5 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 2 application description 2.1 application circuits 2.1.1 application circuits pin ncs: terminate with gnd for uart-mode only, oth erwise is used internal pull-up for spi-mode. pin vsupply: terminate with gnd if ldo is not used. pin vg: terminate with gnd if ldo is not used. pin cp1: no termination (open) if charge pump is no t used. pin cp2: no termination (open) if charge pump is no t used (must not be connected to gnd!!!). pin csync: short to vbus for asynchronous mode. the csync voltage can be supplied on pin csync (if available on ecu) without using the charge pump. this option is not shown here. atic158 c l c e r e 2 ch1_sensor 1 wiring c l l w / 2 c w c e r e 2 sif 4 sif 3 sif 2 sif 1 z s ecu l w / 2 r w / 2 r w / 2 ch4_sensor 1 wiring l w / 2 c w z s l w / 2 r w / 2 r w / 2 ch4_sensor 2 z s vs u pp l y c bus vb u s vg v s u p p l y ( eg . battery ) c g emc filter (tbd) ncs sclk sdo _ txd sdi _ rxd cp 1 cp 2 csync c s y n c c cp o p t i ona l : v c s yn c g n d a g n d d trig vdd nres c dd g n d p v dd power supply & reset c spi c emc r emc nmos k c sync e521.41a c emc r emc figure 2.1.1-1: application circuit with ldo elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 6 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 c sync atic 158 c l c e r e 2 ch1_sensor 1 wiring c l l w / 2 c w c e r e 2 sif 4 sif 3 sif 2 sif 1 z s ecu l w / 2 r w / 2 r w / 2 ch4_sensor 1 wiring l w / 2 c w z s l w / 2 r w / 2 r w / 2 ch4_sensor 2 z s vs u pp l y c bus vb u s vg v s u p p l y ( eg . battery ) cp 1 cp 2 csync c s y n c c cp o p t i ona l : v c s y n c g n d a g n d d power supply & reset vdd c dd g n d p v bus _ sup v dd ncs sclk sdo _ txd sdi _ rxd trig c uart nres e521.41a figure 2.1.1-2: application circuit with vbus suppl ied from ecu table 2.1.1-1: application circuit electrical param eter description condition symbol min typ max unit capacitance at vdd c vdd 100 220 nf ecu bus capacitance c e 15 35 nf ecu resistor r e2 2.0 satellite capacitance c l 2.2 nf total bus capacitance c e +c l_x (x=1..3) 25 107 nf ldo output capacitor ceramic capacitor, esr<=100m c bus 4.7 20 f charge pump fly capacitor ceramic capacitor; esr <= 100m c cp 270 nf charge pump storage capacitor ceramic capacitor; esr <= 100m c sync 14.1 20 f v supply emc capacitor c emc 220 nf v supply emc resistor r emc 100 single wire resistance r w /2 0.5 wire inductance 2*(l w /2) 0 8.7 h wire capacitance c w 0 600 pf elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 7 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 the device can be supplied via pin v supply with an appropriate voltage. this voltage supplies an external nmos transistor that is driven by an internal ldo via th e pin v g . the following external nmos transistor are recommen ded: ? irfz24ns, ? buk7635-55a, ? hufa76409d3st, ? sqd15n06-42l. the stability of the output voltage can be achieved with an external compensation capacitor c k connected between pin v g and agnd. in the following table is shown a suitab le compensation capacitor c k : table 2.1.1-2: recommended compensation capacitor transistor c k irfz24ns 100nf-220nf buk7635-55a 100nf-220nf hufa76409d3st 100nf-220nf sqd15n06-42l 100nf-220nf elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 8 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 3 functional safety 3.1 functional safety requirements the device fulfils the functional safety requiremen t up to asil-level c (system) according to iso 2626 2, depending on the safety mechanisms used. 3.2 fmeda the following toplevel safety requirements were ana lysed with fmeda method: ? tsr1: transceiver shall avoid transmission of corru pted data to the micro controller interface ? tsr2: transceiver shall avoid storage of corrupted safety related data 3.2.1 safety measures mandatory to reach asil level c table 3.2.1-1: mandatory safety mechanisms for asil c derived from fmeda safety mechan- ism ic / system level description sm1 ic synchronous decoding of input data in manchest er decoder with fixed baud rate, fixed frame length and fixed bit count. decod ing errors will be indicated in the error status and potentially corrupted data will be invalidated. sm2 ic data consistency check using parity bit or crc error detection mechanism. note: these mechanisms must be enabled by interface configuration options from system level. sm3 system observe failure rate of manchester decoder or parity/crc errors on system level in order to detect channels with latent fault s that could degrade the robustness of decoding or even cause spurious data corruption. sm4 system / ic internal supplies and references are monitored cyclically with a sampling interval of typ. 2ms. diagnosis block has a separat e reference voltage gener- ation independent from the reference of analyzed si gnals. supervisor function is implemented for the following signals: v bus , v csync , v sif1 , v sif2 , v sif3 , v sif4 , vdd, v dd_int , v cp_gate . sm5 system data consistencies check using crc error d etection mechanism for spi and uart. sm6 system configuration data written to registers of the ic shall be (cyclically) verified by reading them back. available configuration lock mec hanisms shall be used. sm7 system compare the spi response with the command ( address, command,chid,bid, except frame data, register data & xcrc) sm8 system compare the frame id, ch id (if not all ch configurations are same) with respect to the configuration & calculate and compar e the 3-bit crc/parity for the sensor data sm9 system if interface/asic error indicated, read th e error status registers sm10 system if start-or stop bit in uart is not detec ted in time uc can detect uart error on transceiver sm11 system loop back diagnosis: check digital data p rocessing (manchester decoder / data latch / mux / xcrc / uart/spi). elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 9 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 4 operating conditions stresses beyond these absolute maximum ratings list ed below may cause permanent damage to the device. these are stress ratings only; operation of the device at these or any other conditions beyond those listed in the opera- tional sections of this document is not implied. ex posure to absolute maximum rated conditions for ext ended peri- ods may affect device reliability. all voltages ref erred to v(gnd). currents flowing into terminals ar e positive, those drawn out of a terminal are negative. 4.1 absolute maximum ratings table 4.1-1: esd requirements no. description condition symbol min max unit 1 esd according human body model (hbm), q100-002 for pins sifx; vsupply; (100pf/1.5k ) esd pins sifx,vsuppl y 4000 v 2 esd according human body model (hbm), q100-002 for all other pins; (100pf/1,5k ) esd all other pins 2000 v 3 esd according charged device model (cdm), q100-011 corner pins esd corner pins cdm 750 v 4 esd according charged device model (cdm), q100-011 non-corner pins esd non corner pins cdm 450 v 5 input voltage range (supply from ecu) v suppply -0.3 40 v 6 vbus voltage range v bus -0.3 40 v 7 nmos gate voltage at pin v g v g -0.3 40 v 8 voltage of charge pump fly cap. - negative pin v cp1 -0.3 40 v 9 voltage of charge pump fly cap. - positive pin v cp2 -0.3 40 v 10 voltage of charge pump storage capacitor or csync voltage supply (from ecu) v sync -0.3 40 v 11 voltage at sensor interface x=1-4 v sif_x -0.3 40 v 12 supply voltage for analog blocks and digital i/o pins v dd -0.3 19 v 13 voltage of digital input pins v in_dig -0.3 19 v 14 voltage of the digital outputs pins v out_dig -0.3 19 v 15 voltage of nres and testmode pin v nres -0.3 19 v 16 junction temperature t j -40 150 o c 17 storage temperature t stg -40 125 o c 18 ambient operating temperature range t amb -40 125 o c 19 thermal resistance (junction-ambient) (refer to application notes of qfn-packages, thermal con- nection of exposed die pad very important) r tja 23 k/w elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 10 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 4.2 recommended operating conditions parameters are guaranteed within the range of recom mended operating conditions unless otherwise specif ied. all voltages are referred to ground (0v). currents flowing into the circuit have positive values. the first electrical potential connected to the ic must be gnd. (if not specified specify timing seque nce of electrical contacts.) table 4.2-1: recommended operation conditions no. description condition symbol min typ max unit 1 input voltage range at pin v supply 1) application with ldo and external nmos transistor; low voltage mode; v supply_lp 5.3 19 v 2 input voltage range at pin v supply 1) application with ldo and external nmos transistor; standard voltage mode; v supply_std 6.95 19 v 3 input voltage range at pin v supply 1) application with ldo and external nmos transistor; increased voltage mode; v supply_inc 8.0 19 v 4 input voltage range at pin v bus limited range 2) application with (externally gen- erated) available v bus voltage; @ i sifx_op =0- 25ma ldo is disabled v bus_sup_lr 4.6 5.05 v 5 input voltage range at pin v bus full range 3) application with (externally gen- erated) available v bus voltage; @ i sifx_op =0- 65ma ldo is disabled v bus_sup_fr 5.05 11 v 6 v bus voltage ripple; 50hz 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 5 detailed electrical specification 5.1 analog part 5.1.1 supply table 5.1.1-1: current consumption: electrical para meter table no. description condition symbol min typ max unit 1 i vsupply quiescent current consumption *) 1) application with ldo disabled i vsupply_q 15 a 2 i vsupply current consumption operating 1) application with ldo enabled i vsupply_op 0.1 1 ma 3 i vbus quiescent current consumption application with available v bus voltage; interfaces off i vbus_q 1 4 ma 4 i vbus current consumption operating application with available v bus voltage; interfaces on; without load; i vbus_op 6 14 ma 5 i csync quiescent current consumption application with available v csync voltage; interfaces on; without load; i csync_q 0.05 5 ma 6 logic supply operating current vdd=5.5v;nre s=0v i vdd_off 4 10 ma 7 logic supply operating current vdd=5.5v;nre s=vdd i vdd_on 1 10 ma *) not tested in production 1) i vsupply is the current consumption of the pin v supply 5.1.1.1 ldo control block 5.1.1.1.1 electrical parameter of ldo table 5.1.1.1.1-1: electrical parameter table of ld o no. description condition symbol min typ max unit 1 stabilized output voltage of ldo at pin v bus 1) low power mode; 5ma<=i load_bus < =350ma; 5.3v<=v supply <= 19v v bus_lp 5.15 - 2% 5.15 5.15 + 2% v 2 stabilized output voltage of ldo at pin v bus 1) standard power mode; 5ma<=i load_bus < =350ma; 6.95v<=v supply < =19v v bus_std 6.65 - 3% 6.65 6.65 + 3% v elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 13 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 no. description condition symbol min typ max unit 3 stabilized output voltage of ldo at pin v bus 1) increased power mode; 5ma<=i load_bus < =350ma; 8.0v<=v supply <= 19v v bus_inc 7.7 - 3% 7.7 7.7 + 3% v 4 input voltage ripple rejection ratio for low frequencies *) 50hz<=f<=20kh z; v supply_ac =4v pp ; v supply_dc >9v; c bus =4.7f;vbu s=6.65v-setting 5ma<=i bus <=350 ma; v bus_rr_lf 40 db 5 input voltage ripple rejection ration for high frequencies *) 100khz<=f<=50 0khz; v supply_ac =400m- v pp ; 5.6v<=v supply <= 6.4v; c bus =4.7f;vbu s=5.15v-setting 5ma<=i load_bus < =350ma; v bus_rr_hf 20 db 6 line regulation ( v bus voltage for variable v supply voltage) i load_bus is con- stant during test: 5ma<=i load_bus < =350ma; v supply varies: 5.6v<=v supply <= 19v v bus_lir -25 0 25 mv 7 load regulation ( v bus voltage for variable i load_bus current) v supply is con- stant during test: 5.6v<=v supply <= 19v;i load_bus var- ies during test: 5ma<=i load_bus < =350ma v bus_lor -25 0 25 mv 8 v bus voltage overshoot *) v bus_os 10 % 9 v bus voltage start-up time *) 2) t start_ldo 2) 10 internal charge pump for ldo ldo charge pump output voltage v cp_gate 10 19 v *) not tested in production 1) trimmed 2) start-up time t start_ldo can be calculated by following formula: t start_ldo =(v th +v gs_eff )*c k /i vg_drv ; for v th and v gs_eff see nmos transistor data sheet; c k is the compensations capacitor connected between v g and agnd; i vg_drv is the driver charge current. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 14 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 5.1.1.1.2 electrical parameter control voltage table 5.1.1.1.2-1: gate control voltage at pin v g no. description condition symbol min typ max unit 1 nmos gate voltage at pin v g operating v supply =5.3v v g_on v bus + 4.5 v 2 nmos gate voltage at pin v g non operating r dg <=500k between v g and v supply , 250a current sink at pin v bus (source) v g_off 1 v 3 pull down current in off condition i vg_pd 30 50 70 a 4 clamp voltage v g - v bus *) v gs_clamp 7 13 v 5 driver capability i vg_drv 50 80 100 a *) not tested in production 5.1.1.2 charge pump for sync voltage table 5.1.1.2-1: electrical parameter table of the charge pump for sync voltage no. description condition symbol min typ max unit 1 charge pump output voltage at pin csync without load *) i load =0ma v csync_no_ld 2*v bus -1.35v 2*v bus v 2 charge pump output voltage at pin csync in low power mode v bus =5.05v; i load =25ma v csync_lp 8.65 10.1 v 3 charge pump output voltage at pin csync in low power mode v bus =5.05v; i load =28ma (7ma per sifx) v csync_lp 8.6 10.1 v 4 charge pump output voltage at pin csync in standard mode v bus =6.45v; i load =28ma (7ma per sifx) v csync_std 11.35 12.9 v 5 charge pump output voltage at pin csync in increased mode v bus =7.47v; i load =28ma (7ma per sifx) v csync_inc 13.34 14.94 v 6 start-up time for voltage at pin csync *) test condition: 80%*v sync at t start_cp_sync ; without load at pin v sync ; t start_cp_csync 3 ms *) not tested in production 5.1.2 por and power-up sequence table 5.1.2-1: electrical parameter table of por no. description condition symbol min typ max unit 1 power on reset threshold value related to vdd v por_on 2.3 2.9 v 2 power off reset threshold value related to vdd v por_off 2.2 2.7 v 3 power on reset hysteresis *) v por_hys 0.1 0.3 v 4 minimum time nres=low *) t nres_low 1 10 s 5 power on reset delay time *) 1) at power-up of v dd_int t por_d_lh 50 s elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 15 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 no. description condition symbol min typ max unit 6 power off reset delay time *) t por_d_hl 0.5 s 7 input threshold nres low *) v nres_low 0.8 v 8 input threshold nres high *) v nres_high 2 v 9 pull down resistor nres r nres_pull_down 70 100 130 k *) not tested in production 1) the output voltage of the internal vdd-regulator 5.1.3 psi5 interface 5.1.3.1 interface driver table 5.1.3.1-1: electrical parameter table of the interface driver no. description condition symbol min typ max unit 1 voltage at pin sifx (x=1-4), low power mode *) low voltage mode; test condition for v sifx_min measure- ment: v bus =5.05v; i sifx_op =65ma and v bus is supplied dir- ectly v sifx_lp_vbus_min 4.543 v bus v 2 voltage at pin sifx (x=1-4), low power mode *) low voltage mode; v bus =4.6v..5.05v; test condition for v sifx_min measure- ment: v bus =4.6v; i sifx_op =25ma and v bus is supplied dir- ectly v sifx_lp 4.405 5.05 v 3 voltage at pin sifx (x=1-4), common mode *) standard mode; condition for v sifx_min measure- ment: v bus =6.45v; i sifx_op =65ma and v bus is supplied dir- ectly v sifx_std 5.943 v bus v 4 voltage at pin sifx (x=1-4), common mode *) increased mode; condition for v sifx_min measure- ment: v bus =7.47v; i sifx_op =65ma and v bus is supplied dir- ectly v sifx_inc 6.963 v bus v 5 resistance between pin v bus and pins sifx i sifx_op =65ma, including temperat- ure drift and long term drift r vbus_sifx 4.5 7.8 *) not tested in production elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 16 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 5.1.3.2 over current detection and limitation table 5.1.3.2-1: electrical parameter table of the over current detection and limitation no. description condition symbol min typ max unit 1 sensor interface current limitation i lim_sifx -130 -100 -75 ma 2 threshold value for detection of scg "hard short"(low impedance to gnd) *) 1) i sifx_hash 200 ma 3 activation time for over current limitation at pin sifx at "hard short" *) t sifx_ hash_act 300 ns 4 over current switch off delay *) t sifx_ lim_act 491 544 566 s 5 sifx over current start up delay (default value:asic_cnfg_3:bl_channel_1- 4=0000) *) t oc_sifx_5ms 5.007 5.248 5.458 ms 6 sifx over current start up delay(asic_cnfg_3:bl_channel_1- 4=1111) *) t oc_sifx_10ms 10.014 10.464 10.882 ms *) not tested in production 1) scg:short to gnd 5.1.3.3 reverse current detection and limitation 5.1.3.3.1 reverse current flow from sifx to vbus table 5.1.3.3.1-1: electrical parameter table of th e reverse current detection and limitation (revese current flow from sifx to vbus) no. description condition symbol min typ max unit 1 reverse current into sifx-pin in on-state equal to v rev_trig /r vbus- sifx i sifx_rev_on 200 ma 2 reverse current into sifx-pin in off-state *) i sifx_rev_off 1 ma 3 threshold value for detection of the reverse current 1) i sifx_rev_thr 10 30 60 ma 4 activation time for reverse protection at pins sifx *) t sifx_rev_act 500 ns 5 sifx reverse current shut-off activation time (deglitcher) *) t sifx_rev_cur 61 96 100 s *) not tested in production 1) v rev_trig =v bus -v sifx in short to v bat condition 5.1.3.3.2 reverse current flow from sifx to csync table 5.1.3.3.2-1: electrical parameter table of th e reverse current detection and limitation (reverse current flow from sifx to csync) no. description condition symbol min typ max unit 1 threshold value for detection of the reverse current i csync_rev_thr -100 -4 ma elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 17 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 5.1.3.4 data comparator table 5.1.3.4-1: electrical parameter table of the data comparator no. description condition symbol min typ max unit 1 data comparator threshold low->high transition low power mode i comp_th_lp_lh -8.3 -6.3 -4.3 ma 2 data comparator threshold high->low transition low power mode i comp_th_lp_hl -7.7 -5.7 -3.7 ma 3 data comparator threshold low->high transition common mode i comp_th_com_lh -16.6 -12.6 -8.6 ma 4 data comparator threshold high->low transition common mode i comp_th_com_hl -15.4 -11.4 -7.4 ma 5 data comparator hysteresis *) low power mode i comp_hys_lp 0.6 ma 6 data comparator hysteresis *) common mode i comp_hys_com 1.2 ma 7 data comparator filter time (deglitcher) *) manchester code pattern 125kbps; 2bit deglitcher; res- olution 250ns; i data_dgl_lf 480 750 ns 8 data comparator filter time (deglitcher) *) manchester code pattern 189kbps; 2bit deglitcher; res- olution 167ns; i data_dgl_hf 320 500 ns *) not tested in production 5.1.3.5 sync pulse generation 5.1.3.5.1 sync pulse generation dc-parameter table 5.1.3.5.1-1: sync pulse generation dc-paramet er no. description condition symbol min typ max unit 1 sync slope reference voltage *) referenced to v sifx ; t2 defined by v t2 v t0 0.5 v 2 lower boundary of sync signal sustain voltage *) low power mode; referenced to v sifx ; t2 defined by v t2 v t2_lp 2.5 v 3 lower boundary of sync signal sustain voltage *) common mode; referenced to v sifx ; v t2_com 3.5 v 4 upper boundary of sync signal sustain voltage low power mode v t3_lp 2.7+v s ifx 3.7+v s ifx 4.3+v s ifx v 5 upper boundary of sync signal sustain voltage common mode v t3_com 4.2+v s ifx 4.8+v s ifx 5.5+v s ifx v 6 ripple of voltage v t3 (supply rejection between pins csync and sifx) *) test condition: t=close to end of short sync signal =>t=t0+15 s; v t3_rippple 100 mv pp 7 current limitation during sync pulse slope *) i csync_lmt -210.0 -150.0 -110.0 ma 8 csync voltage drop between pin csync and sifx v csync_dr 0.8 v *) not tested in production elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 18 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 5.1.3.5.2 sync pulse generation ac parameter table 5.1.3.5.2-1: sync pulse generation ac-paramet er no. description condition symbol min typ max unit 1 sync slope rising slew rate transition from v t0 to v t2 ; 24nf<=c bus <=10 7nf; 4ma<=i sifx <=35 ma sr rise 0.43 1.5 v/s 2 sync slope falling slew rate transition from v t2 to v t0 ; 24nf<=c bus <=10 7nf; 4ma<=i sifx <=35 ma sr fall -1.5 v/s 3 reference time for sync slope *) 1) reference time base defined at v t0 t 0 0 s 4 sync signal earlist start *) 1) t 1 -1 s 5 sync signal sustain time *) 1) short sync pulse t 0 3 16 s 6 sync signal sustain time *) 1) long sync pulse t 1 3 43 s 7 discharge time limit *) 1) short sync pulse t 0 4 35 s 8 discharge time limit *) 1) long sync pulse t 1 4 62 s 9 minimum idle time of tx_len counter *) t tx_len_idle 32 s *) not tested in production 1) see timing diagram figure 6.1.3.6-1 5.1.3.6 sync pulse generation by pin trig table 5.1.3.6-1: trigger via pin trig no. description condition symbol min typ max unit 1 schmitt-trigger - low input level at pin trig v smt_l 0.8 v 2 schmitt-trigger - high input level at pin trig v smt_h 2 v 3 trigger pulse at pin trig - short sync pulse *) 70% of rising slope to 30% of falling slope t trig_sh_pulse 10 15 20 s 4 trigger pulse at pin trig - long sync pulse *) 70% of rising slope to 30% of falling slope t trig_lng_pulse 40 45 50 s 5 trigger pulse rise and fall *) transition from 20% to 80% (and vice versa); t trig_ri/ra 50 ns 6 trigger pulse filter time *) 3bit deglitcher; resolution 1s t dgl_trig 4.72 5 5.2 s 7 delay counter to distinguish between short/long sync pulse *) t dly 30 s elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 19 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 no. description condition symbol min typ max unit 8 sync pulse delay timer *) step size = 2s; configuration via uart/spi with 10bit t sync_dly 0 8/f clk_i nt *(2 10 - 1) s 9 sync pulse delay from counter *) t sync_dly_cnt 32/f clk_ int s 10 time between two sync pulses on different sifx channels *) t sync_rep1 0 s 11 sync pulses repetition time on the sifx channel *) limited if charge pump is used; applies for i sifx_q =4...-19ma (standard cur- rent) t sync_rep2_std 200 s 12 sync pulses repetition time on the sifx channel *) limited if charge pump is used; applies for i sifx_q =4...-35ma (extended cur- rent) t sync_rep2_ext 300 s 13 pull down resistor pin trig, applies for voltage vtrig<3.3v r trig_pull_down 70 100 150 k 14 pull down current pin trig, applies for voltage vtrig>3.3v i trig_pull_down 10 60 a *) not tested in production 5.1.4 clock generation table 5.1.4-1: electrical parameter table of the in ternal oscillator no. description condition symbol min typ max unit 1 internal oscillator clock frequency 1) f clk_int 11.52 12.00 12.48 mhz 2 duty cycle of f clk_int *) dc clk_int 40 60 % *) not tested in production 1) trimmed 5.1.5 diagnosis 5.1.5.1 adc voltage measurements table 5.1.5.1-1: electrical parameter table of the adc. no. description condition symbol min typ max unit 1 positive reference voltage v refh 2.6 2.7 2.75 v 2 offset measurement of v bus diagnosis voltage of adc output v bus =4.6v .. 11v v bus_offset -450 250 mv 3 gain measurement of v bus diagnosis voltage of adc output v bus =4.6v .. 11v v bus_gain 0.94 1 1.06 v bus 4 offset measurement of v csync diagnosis voltage of adc output v csync =8v .. 33v v csync_offset -1.8 1.4 v 5 gain measurement of v csync diagnosis voltage of adc output v csync =8v .. 33v v csync_gain 0.85 1 1.15 v csync elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 20 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 no. description condition symbol min typ max unit 6 offset measurement of vdd diagnosis voltage of adc output vdd=3.0v .. 5.5v vdd offset -400 200 mv 7 gain measurement of vdd diagnosis voltage of adc output vdd=3.0v .. 5.5v vdd gain 0.93 1 1.07 vdd 8 offset measurement of v sifx diagnosis voltage of adc output v bus =4.6v .. 11v v sifx_offset -450 250 mv 9 gain measurement of v sifx diagnosis voltage of adc output v bus =4.6v .. 11v v sifx_gain 0.94 1 1.06 v bus 10 measurement of v cp_ldo diagnosis voltage of adc output v suppply =5.3v,v b us =7v v cp_ldo 10.2 12.2 14.2 v 11 measurement of v cp_ldo diagnosis voltage of adc output v suppply =6.95v,v bus =7v v cp_ldo 12.2 14.2 16.2 v 12 measurement of v cp_ldo diagnosis voltage of adc output v suppply =8v,v bus =7v v cp_ldo 13.2 15.2 17.2 v 13 measurement of v dd_int diagnosis voltage of adc output vdd=3.3v v dd_int 3.0 3.2 3.4 v 14 measurement of v dd_int diagnosis voltage of adc output vdd=5v v dd_int 3.0 3.2 3.4 v 5.1.5.2 over temperature monitoring (ot) table 5.1.5.2-1: electrical parameter table of the over temperature sensing: no. description condition symbol min typ max unit 1 junction temperature threshold value; low- >high transition *) t j_hi 154 165 174 c 2 junction temperature threshold value; high- >low transition *) t j_li 145 155 165 c 3 junction temperature hysteresis *) t j_hys 10 c 4 over temperature filter time (deglitcher) *) t ot 8.1 ms *) not tested in production 5.1.5.3 v bus over voltage monitoring table 5.1.5.3-1: vbus over voltage monitoring no. description condition symbol min typ max unit 1 v bus over voltage comparator - threshold value v bus_ov_thr 11.8 13 v 2 v bus over voltage comparator - hysteresis *) v bus_ov_hys 0.5 v 3 v bus over voltage filter time (deglitcher) *) t vbus_ov 61 96 100 s *) not tested in production elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 21 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 5.2 digital part 5.2.1 spi 5.2.1.1 dc electrical parameter table of spi ios table 5.2.1.1-1: dc electrical parameter table of t he digital inputs and outputs no. description condition symbol min typ max unit 1 input threshold low sdi_rxd, ncs,sclk v thdig_l 0.8 v 2 input threshold high sdi_rxd, ncs,sclk v thdig_h 2 v 3 output voltage sdo_txd low i sdo_txd_l =3.2ma v sdo_txd_l 0.4 v 4 output voltage sdo_txd high i sdo_txd_h =-2ma v sdo_txd_h v dd - 0.4v v dd v 5 pull up resistor ncs r ncs_pull_up 70 100 130 k 6 pull up resistor rxd r sdo_rxd_pull_up 70 100 130 k 5.2.1.2 ac electrical parameter table of spi i/os table 5.2.1.2-1: electrical parameter table of spi no. description condition symbol min typ max unit 1 spi frequency *) f sclk 0 5 mhz 2 sdo_txd rise and fall time *) 20pf...150pf load t sdo_trans 5 35 ns 3 minimum time clk=low *) t clh 75 ns 4 minimum time clk=high *) t cll 75 ns 5 propagation delay (sclk to data at sdo active) *) 150pf load; from sclk=2.3v to sdo=0.5*v dd_sup , applies for 3.3v/5v; t pcld 50 ns 6 ncs low to output sdo active *) 150pf load t csdv 75 ns 7 sclk low before ncs low (setup time sclk to ncs change h/l) *) t sclch 75 ns 8 sclk change l/h after ncs=low *) t hclcl_app 600 ns 9 sdi input setup time (sclk change h/l after sdi data valid) *) t scld 15 ns 10 sdi input hold time (sdi data holdafter sclk change h/l) *) t hcld 15 ns 11 sclk low before ncs high *) t sclcl 100 ns 12 sclk high after ncs high *) t hclhc 100 ns 13 ncs l/h to sdo@high impedance *) t pchdz 75 ns 14 ncs min. high time between two consecut- ive commands *) t on_ncs 700 ns 15 ncs filter time *) t fncs 10 40 ns *) not tested in production elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 22 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 6 functional description 6.1 analog part 6.1.1 supply various supply voltage concepts are supported by th e device due to the various possible applications. the device is supplied via the pin v supply with an appropriate voltage. this voltage supplies an external transistor that is driven by an internal ldo via the pin v g . the output of the external transistor is fed back via the pin v bus to the ldo con- trol block. if an external nmos transistor is used, the interna l error amplifier has to be compensated with an ext ernal com- pensation capacitor c k connected between v g and agnd. for low supply voltages v bus on the ecu, the asic can be supplied directly at pin vbus with the voltage p rovided by v supply , when no voltage drop between the pins v sup- ply and v bus can be accepted. in this case the ldo must be disa bled. the voltage v csync , which is necessary for providing the sync pulse is generated in the block charge pump for sync voltage (cp). the voltage v csync is available at the pin csync. alternatively, the csync voltage can be supplied directly at the pin csync with exte rnal voltage v csync . the v csync charge pump must be disabled in this case. the following table gives an overview of possible supply voltage concepts, which can be chosen via spi or uart commands. table 6.1.1-1: overview supply voltage concepts config options v dd v supply v bus v csync ldo enabled cp enabled a vdd supplied directly v supply supplied directly generated by ldo generated by charge pump yes yes b vdd supplied directly v supply supplied directly generated by ldo v sync supplied from ecu yes no c vdd supplied directly n.a. v bus supplied dir- ectly generated by charge pump no yes d vdd supplied directly n.a. v bus supplied dir- ectly v sync supplied from ecu no no 6.1.1.1 ldo control block a low drop out regulator (ldo) with external nmos a nd compensation capacitor c k is implemented to generate a stable v bus voltage out of the input voltage v supply . a ldo control circuit is implemented to drive the external nmos transistor. three voltage levels for v bus are configurable via bit combination asic_cnfg_1[v _bus] (see descrip- tion of register asic_cnfg_1 for details). the ldo control circuit is disabled by default value asic_cnfg_1[v_bus]="00". the voltage loop has be to compensated with an external compensation capacito r c k at pin v g for stability reasons. the ldo charge pump provide s an appropriate voltage v cp_gate for control of the external nmos transistor at pin v g . a gate source voltage clamping to the voltage v gs_clmp is implemented. 6.1.1.2 charge pump for sync voltage a charge pump is used to generate the sync pulse vo ltage from the voltage vbus. the charge pump consis ts of two external capacitors, the fly capacitor cp conne cted to pins cp1 and cp2, the storage capacitor csy nc con- nected to pin csync, two diodes and two high voltag e switches inside the ic. the charge pump is config urable via bit asic_cnfg_3[en_cp_sync] (see description of reg ister asic_cnfg_3). ? en_cp_sync='0' means disabled ? en_cp_sync='1' means enabled the charge pump circuit is disabled for the asynchr onous mode. if the charge pump is not used, then it is not allowed to connect the pin csync with ground. the d iode path from v bus to c sync will result in high current and destruction of ic. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 23 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 6.1.2 por and power-up sequence the por-block observes the voltages v dd_int , v ana , nres, v agnd and v pgnd . it generates the por-signal. during the power up time, the following actions take place : ? the voltage regulators v dd_int and v ana provide the voltage v dd_int and v ana ? the bandgap/biasing block provides the voltage v bg and the bias ? the internal oscillator starts up and provides a st able clock frequency for the digital part after pow er-up time, the rising edge of the nres determines the interface mo de (spi/uart), depending on the state of the pin nc s. when ncs is low the uart interface is selected. whe n ncs is high the spi is chosen. during the power u p time is not allowed to change the logic level of nr es. 6.1.3 psi5 interface 6.1.3.1 interface driver each of the four interfaces provide a voltage v sifx and a current i sifx for the connected satellite sensors by "switch- ing" voltage v bus to the pin sifx via internal transistor switches a nd shunt. the interfaces are short-circuit protecte d to v bat and gnd. the four interfaces operate independent f rom each other. the interfaces can be en-/disabled via an uart/spi command with the bits en_chx , describe d in register asic_cnfg_3. the default state of the inter- face is disabled. the current sensing block include s an i base tracking function and the data-comparator. any time a channel is enable by [en_chx], a blankin g time is started. during this delay time t sifx_blanking , the manchester decoder, sync pulse generator and overcu rrent filter time t oc_sifx are disabled. no channel enable possible if following error bits are set to '1': - error_status_1[vbus_ov] - error_status_x[rev_cur_chx] if rev_cur_ch_dis='1' - error_status_x[oc_chx] - error_status_1[diag_ot] 6.1.3.2 over current detection and limitation the circuit provides an over current limitation and protection of the interfaces. the current limitati on for i sifx is imple- mented with a voltage measurement over the shunt re sistor r sh and with the control of the transistor t2. if the cur- rent i sifx exceeds the threshold current i lmt_sifx , the comparator output signal i sifx_oc_det is set to high. this signal is filtered in the digital block by a deglitcher with the filter time t sifx_lim_act , latched in the register error_status_x[oc_chx] and the appropriate channel is disabled ,that means the affected en_chx bits ar e reset by the device automatically. to switch on the channel again it is essential to read out the appr opriate error register ("clear on read"). to ensure proper over c urrent detection, the threshold value for overcurre nt limitation is higher than the over current detection threshold. in order to avoid over current switch off during st art up (enable of channels), a blanking time of t oc_sifx_5ms resp. t oc_sifx_10ms is implemented. during this time the over current switch off is disabled. the blanking time can be pr o- grammed in the register asic_confg_3 bl_channelx. 6.1.3.3 reverse current detection and limitation the ic provides two different paths of the reverse current protection: ? from pin sifx to pin vbus ? from pin sifx to pin csync 6.1.3.3.1 reverse current flow from sifx to vbus the circuit provides the reverse current detection from sifx pin to vbus pin. the reverse current dete ction is implemented with a voltage measurement over the shu nt resistor r sh (like described in the chapter over current detection). if a reverse current is detected the co mparator output signal will be set to high. the sig nal will be deglitched and latched in the register error_status _x[rev_cur_chx]. the affected channel will be disab led if configuration bit asic_cnfg_2 [rev_cur_ch_dis] i s set to high and the affected en_chx bits are rese t by the device automatically. to switch on the channel again it is essential to r ead out the appropriate error register ("clear on r ead"). elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 24 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 6.1.3.3.2 reverse current flow from sifx to csync the circuit provides the reverse current detection from pin sifx to pin csync. the reverse current det ection is implemented with a mos-transistor. the reverse curr ent protection circuit stops the reverse current fr om sifx pin to csync pin when sifx becomes higher then csync. 6.1.3.4 quiescent current threshold tracking the quiescent current of the circuit is measured an d adapted continously during during operation, to a void corrup- ted data transmission because of drift or aging pro cesses. 6.1.3.5 data comparator the satellite sensors modulate the current in order to realize a manchester coded data transmission. the "low" level of the current is represented by th e quiescent current i sat_q_range of the sensor, while a "high" level is created by switching on a current sink to the line, which increases the current to i sat_op . a current transition in the middle of the bit time represents the logical value of the transferred dat a. a "high cur- rent-low current" transition stand for a logical '1 ', a "low current-high current" transition for a lo gical '0'. this current can be detected by measuring the volta ge drop via an internal shunt. the current threshol d is automat- ically adapted to the quiescent current of the sens ors. the threshold value is configured with register asi c_cnfg_1[ is_chx] with 1bit per sifx (changed indivi dually). ? ? the default value is is='0' (common mode). is='1' m eans the threshold value for low power mode is choo sen (see register description of asic_cnfg1). isat isat_op isat_th isat_q_range ? i tbit bit1 ?0? bit2 ?1? bit3 ?1? t figure 6.1.3.5-1: current modulation elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 25 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 6.1.3.6 sync pulse generation for psi5 synchronous mode, the ic generates the syn c pulse to synchronize the sensors. during sync pul se the voltage level at pins sifx will be increased fo r a defined time and then decreased before the sens or to ecu communication (current modulation) starts. the sync pulse is shaped to limit emissions. the sync volta ge is either generated by sync pulse charge pump or suppl ied from external via pin csync. the voltage level vt3 is configured with the regist er asic_cnfg_1[vsync_v3_chx] with 1 bit per sifx (c hannel individually). the ic provide a reverse protection for the short c ircuit to the battery at the interfaces and current limitation of the sync pulse. the current limitation is active during sync sustain time only. the current limitation is disabled during rising/falling slope to guarantee slope at max. loa d. there are two ways to generate an event triggered s ync pulse: ? by trigger voltage pulse at pin trig ? by uart/spi command phase 1 sync start vtrig vt2 vt0 vce base t1 t0 t2 t 0 3 t 0 4 t 1 3 t 1 4 vce max phase 2 sync slope phase 3 sync sustain phase 4 sync discharge long sync pulse [1] short sync pulse [0] trigger point lower boundary upper boundary vt3 figure 6.1.3.6-1: sync pulse timing diagram elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 26 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 6.1.3.7 sync pulse generation by pin trig following diagram shows the timing requirements for the trigger voltage pulse at pin trig with: ? high time t trig_sh_pulse for a short sync pulse ? high time t trig_lo_pulse for a long sync pulse atic158 timer sync_dly long pulse (t 1 3 + t 1 ) v sifx t sync_dly t trig_lo_pulse v trig (pin trig) example: long sync pulse 70% 30% i_trig_f t dgl_itrig sync_time t ( t dgl_itrig + 1/f clk ) i_trig t dgl_itrig figure 6.1.3.7-1: long sync pulse trigger via pin t rig atic158 timer sync_dly v sifx t sync_dly v trig (pin trig) example: short sync pulse i_trig_f t ( t dgl_itrig + 1/f clk ) i_trig t dgl_itrig sync_time short pulse (t 0 3 + t 1 ) 30% t dgl_itrig t trig_sh_pulse 70% figure 6.1.3.7-2: short sync pulse trigger via pin trig elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 27 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 6.1.3.8 sync pulse generation by uart/spi command following timing diagrams show the sync pulse gener ation triggered by a uart or spi command. sync_dly sync_time short pulse (t 0 3 + t 1 ) long pulse (t 1 3 + t 1 ) v sifx uart stp p d7 ?. d0 srt syncronizer 1/(f clk_ext ) + 4/(f clk_int ) atic158 timer t sync_dly figure 6.1.3.8-1: short sync ptrigger via uart spi sync_dly sync_time short pulse (t 0 3 + t 1 ) long pulse (t 1 3 + t 1 ) v sifx ...sync_pulse spi ncs t sync_dly 3*1/(f clk_int ) atic 158 timer figure 6.1.3.8-2: short sync pulse trigger via spi 6.1.4 clock generation the internal oscillator is the central clock source for the digital part and provides the clock signal required for the internal charge pumps. the oscillator starts up aut omatically as soon as v dd_int and v ana are stable. an external clock has to be supplied via pin sclk f or uart communication. the ratio between external c lock and uart baud rate is 5/1 ( = 5 times oversampling for uart telegrams on sdi_rxd). elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 28 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 6.1.5 diagnosis 6.1.5.1 adc voltage measurements several voltage levels can be measured by the asic with an analog-digital converter for diagnostic pur poses. the digital values will be written into status register s after conversion. these registers can be read out by the micro con- troller via uart/spi. an 8-bit adc (successive approximation register con cept) is implemented for diagnosis purposes. in tot al 9 internal voltages are measured sequentially in a re peating (endless) loop. the measurement of one volt age is called a cycle. steps within a cycle: ? voltage is selected via mux ? adc conversion is performed ? data is transferred into register diagnosis_adc_1_2 to diagnosis_adc_9_10 one sequence is performed within t cyc . each measured voltage is stored in a dedicated re gister. the update rate of the register values is given by number of voltages multiplied with cycle time -> 9 x t cyc .the adc sequence starts with release of reset automatically. for synchronous mode the values at "pin sifx" can vary between v sifx and v t3 , depending whether a sync pulse was generated during conversion time or not. for asynchronous mode the voltage at pin sifx is measured properly. the following table shows the voltage divider ratio of the different voltages. table 6.1.5.1-1: voltage divider ratio voltage divider ratio v bus 1/5 v sync 1/13 v cp_gate 1/7 v sifx 1/5 v dd_int 1/2 v dd 1/3 6.1.5.2 over temperature monitoring (ot) chthe junction temperature is monitored with a temp erature sensor to detect excessive temperature leve ls. if the junction temperature exceeds t j_hi then following protection actions will be processe d automatically: ? all sifx will be disabled -> reset bit asic_cnfg_3[ en_chx]='0' ? the affected en_chx bits are reset by the device au tomatically. to switch on the channel again it is e ssential to read out the appropriate error register ("clear on read"). ? sync pulse charge pump will be disabled -> reset bi t asic_cnfg_3[en_cp_sync]='0' ? over temperature event is latched in status registe r error_status_1[diag_ot] after t ot (clear on read) ? with read of error_status_1[diag_ot], the filter ti mer for t ot is reseted (deglitcher reset), independently of the current error status. ? if the read cycle of error_status_1[diag_ot] is sho rter than t ot , the error_status_1[diag_ot] bit will never be set. ? the channel will not be enabled automatically, if t he error condition disappears. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 29 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 6.1.5.3 v bus over voltage monitoring a comparator for v bus over voltage monitoring is implemented to avoid an y damage of psi5 sensors by exceeding their input voltage range. if vbus exceeds the value of v bus_ov_thr then following protection actions are processed au tomatically: ? all sifx will be disabled -> reset bit asic_cnfg_3[ en_chx]='0' ? the affected en_chx bits are reset by the device au tomatically. to switch on the channel again it is e ssential to read out the appropriate error register ("clear on read"). ? sync pulse charge pump will be disabled -> reset bi t asic_cnfg_3[en_cp_sync]='0' ? the over voltage event is latched in status registe r error_status_1[vbus_ov] after t vbus_ov (clear on read) ? with read of error_status_1[vbus_ov], the filter ti mer for t vbus_ov is reseted (deglitcher reset), independ- ently of the current error status. ? if the read cycle of error_status_1[vbus_ov] is sho rter than t vbus_ov , the error_status_1[vbus_ov] bit will never be set. ? the channel will not be enabled automatically, if t he error condition disappears. 6.1.5.4 leakage to gnd, leakage to v bat and open load the detection of leakage to gnd, leakage to vbat an d open load are implemented in the digital logic, b ased on the ibase tracking function. the digital counter for i base indicates a leakage to gnd for high counter values (high quiescent current) and the actual state is latched in status register error_st atus_x[diag_chx]. for low counter values either a leakage to v bat or an open load condition is indicated (low or no quiescent curret). the actual state is latched in status register erro r_status_x[diag_chx]. the differentiation of leakage to v bat / open load failure has to be done by the micro co ntroller via the status of reverse current protection error_ status_x[rev_cur_chx] ? reverse current protection not active [rev_cur_chx] ='0' -> open load ? reverse current protection active [rev_cur_chx]='1' -> leakage to vbat or via adc voltage measurement at pins sifx (if flag [rev_cur_chx]='0'), ? v sifx = v bus -> open load ? v sifx > v bus -> leakage to vbat 6.1.5.5 gnd loss detection a comparator for gnd loss detection is implemented to detect missing gnd connections. a detected gnd loss results in a reset of the ic. following gnds will be monitored: ? agnd ? pgnd 6.1.5.6 transfer of error- and diagnosis informatio n to controller 6.1.5.6.1 error information all error analog/digital information are flagged in status registers error_status_1 ... error_status _ 10. every error is latched and is cleared by a read req uest by spi or uart. an overall error information is transmitted to the micro controller, included in some frames (see belo w) within bits err[1:0]. for detailed error information the dedica ted status registers shall be read. ? uart: bits err[1:0] included in header (uart frame1 ) ? spi: bits err[1:0] included in the first response f rame (spi frame2) the error information, bits err[1:0], are transmitt ed in following messages to the micro controller: ? uart ? response to read command ? transfer psi5 data ? spi ? responses to commands "cmd_get data_xxbit" elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 30 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 these responses allows the controller to know which kind of an error occurred. (all interface errors, shown in the table below, ar e flagged in registers error_status_3 to error_status_10. register error_status_2 includes an or-combination of all interface errors, one bit per channel. e.g. error_status_2[0] includes the or-combination of bits in registers error_status_3 and error_status_4 (=error information of channel 1).) for detailed information see register table. note : it is recommended to read out register error_status _2 if bit err[0] (interface error) is set in a response of the transceiver to determine which channels are affecte d. in register error_status_2 the four lsbs [3:0] b elongs to channel 4, channel 3, channel 2 and channel 1 an d the appropriate channel bit is set in case of an interface error on the affected channel. afterwards the micro controller shall read the dedi cated registers error_status_3 .. error_status_10 (depend of the affected channels) to get the detail ed error information. there are two detailed error registers avail- able per channel. if bit err[1] (asic error) is set in a message to the micro controller regist er error_status_1 shall be read for more information. it is not recommended to read out the appropriate e rror_status_x with a cycle time of less than 9ms. table 6.1.5.6.1-1: overview of possible error infor mation type of error asic interface ch1-ch4 frame 1-6 error status register error bit flag uart parity error. asic x error_status_1[0] err[1] uart framing error (invalid stop bit). asic x error_status_1[1] err[1] uart/spi invalid command received. asic x error_status_1[2] err[1] uart/spi colli- sion. asic x error_status_1[3] err[1] spi clock error. asic x error_status_1[4] err[1] over temperature shut down. asic x error_status_1[5] err[1] v bus overvoltage. asic x error_status_1[6] err[1] mcd crc/parity error. interface x x ch1: error_status_3[0]/[4]/[8]/[12], error_status_4[0]/[4] ch2: error_status_5[0]/[4]/[8]/[12], error_status_6[0]/[4] ch3: error_status_7[0]/[4]/[8]/[12], error_status_8[0]/[4] ch4: error_status_9[0]/[4]/[8]/[12], error_status_10[0]/[4] ch1: error_ status_2[0] ch2: error_ status_2[1] ch3: error_ status_2[2] ch4: error_ status_2[3] elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 31 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 type of error asic interface ch1-ch4 frame 1-6 error status register error bit flag md framing error (frame too long(short, mc code violation, compensation win- dow violation). interface x x ch1: error_status_3[1]/[5]/[9]/[13], error_status_4[1]/[5] ch2: error_status_5[1]/[5]/[9]/[13], error_status_6[1]/[5] ch3: error_status_7[1]/[5]/[9]/[13], error_status_8[1]/[5] ch4: error_status_9[1]/[5]/[9]/[13], error_status_10[1]/[5] ch1: error_ status_2[0] ch2: error_ status_2[1] ch3: error_ status_2[2] ch4: error_ status_2[3] md no frame received. interface x x ch1: error_status_3[2]/[6]/[10]/[14], error_status_4[2]/[6] ch2: error_status_5[2]/[6]/[10]/[14], error_status_6[2]/[6] ch3: error_status_7[2]/[6]/[10]/[14], error_status_8[2]/[6] ch4: error_status_9[2]/[6]/[10]/[14], error_status_10[2]/[6] ch1: error_ status_2[0] ch2: error_ status_2[1] ch3: error_ status_2[2] ch4: error_ status_2[3] md unexpected frame. interface x x ch1: error_status_3[3]/[7]/[11]/[15], error_status_4[3]/[7] ch2: error_status_5[3]/[7]/[11]/[15, error_status_6[3]/[7] ch3: error_status_7[3]/[7]/[11]/[15, error_status_8[3]/[7] ch4: error_status_9[3]/[7]/[11]/[15, error_status_10[3]/[7] ch1: error_ status_2[0] ch2: error_ status_2[1] ch3: error_ status_2[2] ch4: error_ status_2[3] diagnosis: leakage to gnd / vbat. interface x ch1: error_status_4[9:8] ch2: error_status_6[9:8] ch3: error_status_8[9:8] ch4: error_status_10[9:8] ch1: error_ status_2[0] ch2: error_ status_2[1] ch3: error_ status_2[2] ch4: error_ status_2[3] overcurrent. inter- face x ch1: error_status_4[10] ch2: error_status_6[10] ch3: error_status_8[10] ch4: error_status_10[10] ch1: error_ status_2[0] ch2: error_ status_2[1] ch3: error_ status_2[2] ch4: error_ status_2[3] data buffer config- uration error (width=96bit). interface x ch1: error_status_4[11] ch2: error_status_6[11] ch3: error_status_8[11] ch4: error_status_10[11] ch1: error_ status_2[0] ch2: error_ status_2[1] ch3: error_ status_2[2] ch4: error_ status_2[3] elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 32 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 type of error asic interface ch1-ch4 frame 1-6 error status register error bit flag reverse current. interface x ch1: error_status_4[12] ch2: error_status_6[12] ch3: error_status_8[12] ch4: error_status_10[12] ch1: error_ status_2[0] ch2: error_ status_2[1] ch3: error_ status_2[2] ch4: error_ status_2[3] elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 33 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 6.2 digital part 6.2.1 communication interface to micro controller as interface to the micro controller, either an uar t or spi interface can be selected. the pins for bo th interfaces are shared. the interface is configurable from c ? with rising edge of nres the uart / spi interface i s latched ? depending on state of pin ncs either uart or spi is selected ? ncs = low means uart ? ncs = high means spi following pins are used for uart communication: ? sdi_rxd ? sdo_txd ? sclk following pins are used for spi communication: ? sdi_rxd ? sdo_txd ? sclk ? ncs 6.2.2 manchester decoder the manchester decoder is compliant to psi5 1.3 and 2.1. the following interface diagnosis features ar e suppor- ted: ? wrong data rate ? wrong start bit combination ? wrong number of data bits ? crc or parity failure ? wrong interframe time ? no or unexpected frame 6.2.2.1 manchester data handling and buffer archite cture for each channel are a mcd_data_buffer with a width of 36bits and a data_buffer with a width of 96bits implemented. ? data_buffer (96bit) is used in different configurat ions for uart / spi mode (see figure below). ? data_buffer and mcd_data_buffer will be set to defa ult bit value = '1' if the channel is disabled. ? disabled either by writing bits asic_cnfg_3[en_chx] via uart/spi write_register command or ? by automatically switch-off in an error condition ( e.g. over current error). channel4 channel3 channel2 channel1 mcd (manchester decoder ) psi5 data frame (from sensor ) width = 36bit width = 96bit mcd_ data_buffer data_buffer parallel upload (end of valid frame ) bit upload (with end of decoded bit ) figure 6.2.2.1-1: buffer architecture overview elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 34 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 6.2.2.1.1 uart data buffer uart buffer behavior: ? one frame will be stored ? data will be filled up starting at bit0 (lsb) of bu ffer ? empty bits will be filled up with default bit value = '1' ('1' not used as frame id) ? min data length = fid0...fid2 + err0...err1 + d0... d7 + parity; = 14bit ? max data length = fid0...fid2 + err0...err1 + d0... d27 + crc; = 36bit '''with an appropriate uart baud rate, the ic trans mits the data to the controller without any overwriting.''' psi5 data frame (from sensor) s1 s2 d0 ... dn crc/par d0 ... dn crc/par fid [0..2] err [0..1] mcd shall... -remove start bits - add frame identifier fid [0:2] - add error bits err [0:1] default = ?1' 95 data 0 data_buffer ? uart configuration 13...35 14...36 parallel upload with valid stop condition of mcd (end of valid frame ) manchester decoder mcd_data_buffer lsb msb figure 6.2.2.1.1-1: uart data buffer 6.2.2.1.2 spi data buffer spi data buffer behavior: ? mcd_data_buffer has a length of 36bit; only the con figured nb of bits (according tsx_flen) + err[0:1] + fid[0:2] are uploaded into spi_data_buffer; the remaining bi ts of mcd_data_buffer are filled up (stuffed) with '1'. a spe- cial case occurs for spi_buffer_config =0b00 (48bit ): after upload of mcd_data_buffer, bits [0:35] inc ludes data + stuffing '1', whereas bits [36:47] are stuff ed with '0' (described as don't care bits in figure figure 6.2.3.9.4- 1). this doesn't matters for other spi_buffer_confi g configuration as buffer length is smaller than mcd_data_buffer length. ? the data_buffer has to be configured during ic star t up, by bits chx_cfg7[spi_buffer_config]. the buff er is divided in blocks with equal number of bits. ? data will be filled up starting at lsb of every ind ividual block ? unused buffer identifiers (bid[x]) are filled up wi th value = '1' (per default). a read request will r esult in ? frame identifier - fid[2:0] ='111'-> c can detect t hat no data were written into this block (wrong bid [x] was read). ? error bits - err[1:0] = '11' -> c has to discard (d efault values instead of error information) ? it's mandatory to read block wise via commands spi_ get_data_xxb according the appropriate buffer configuration. this means for spi_buffer_config="11 " the command spi_get_data_16b is mandat- ory. ? after reading, all bits per block will be filled up with default bit value = '1' ? during transfer from mcd_data_buffer to data_buffer , an error is flagged in error_status_4/6/8/10[11] = buff_err_chx if number of bits(mcd_data_buffer) > n umber of bits per bid. in this case no data is tran s- ferred. ? the data_buffer is completely erased (filled up with default value ='1') if a channel is disabled , e.g. by asic_cnfg_3[en_chx]='0', vbus overvoltage, overtemp erature or overcurrent shut down. the number of psi5 data bits (payload) per buffer i dentifier (bid) is shown in the table below for all configurations. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 35 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 figure 6.2.2.1.2-1: spi data buffer if number of frames higher than number of configure d buffers (fid > bid): ? a buffer has to be used for several frames ? controller has to ensure to read buffer data before new data is loaded, otherwise it's overwritten. following example shows buffer configuration chx_cf g7[spi_buffer_config]=0b01 with 4 identical psi5 frames: example: 4 frames, including (fid[0:2] + err[0:1] + d[0:19] + crc); = 28bit chx_cfg7 [spi_buffer_config] frame1 frame2 frame3 frame4 bid[1] 32 63 bid[2] 64 95 bid[0] 0 31 0b01 stuffing 0 27 stuffing stuffing 32 59 64 91 figure 6.2.2.1.2-2: spi data buffer incl. 4 frames table 6.2.2.1.2-1: spi buffer configuration chx_cfg7 [spi_buffer_config] per bid [bit] fid + err [bit] max payload = psi5 data w/o start bits [bit] 0b00 48 * 5 43 0b01 32 * 5 27 0b10 24 * 5 19 0b11 16 * 5 11 *: please note the appropriate spi_get_data_xxb-comman d selected by the number of bits in this column. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 36 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 6.2.2.2 manchester bit encoding 6.2.2.2.1 definition of data edge / compensation ed ge according psi5 standard, a current transition in th e middle of the bit time represents the logical val ue of the trans- ferred data (manchester code) with " high current -> low current" transition for a logical ' 1' , " low current -> high current" transition for a logical ' 0' . within this specification, this transition is calle d data edge ; transitions at start / end of the bits are called compens- ation edge . 6.2.2.2.2 interpretation with manchester decoder the implemented manchester decoder (mcd) state mach ine converts psi5 data (transmitted by sensors in manchester code) into nrz code. the input signal is filtered by the analog datacomp arator. the user is able to configure the time slot in whic h a data edge / compensation edge is accepted via r egister asic_cnfg_1[mcd_data_cmp_windows]. in principle, the default configuration is recommen ded with mcd_data_cmp_windows=0b00. for certain pattern of electro-magnetic disturbers (from environment) the configuration of mcd_data_cm p_win- dows=0b01 could improve immunity by decreasing the data edge window, but reduces the range of mcd duty cycle. 6.2.2.2.3 definition of duty cycle d0 = '0' d1='1' 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 50 16 16 16 16 35 11,2 21 11 11 65 20,8 11 21 21 psi5 frame @ 125kbit/s clock 4mhz duty cycle [%] thigh [nb of s a mpl es of 32] figure 6.2.2.2.3-1: example mcd duty cycle elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 37 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 6.2.2.2.4 decoder error flags the following chapter gives some details about the setting of flags md_perr_chx_fx, md_ferr_chx_fx, md_no_fr_chx_fx and md_unex_fr_chx_fx. frame error 111 000 slot counter 001 psi5 data mcd: valid start bit md_ferr_chx_fx md_ no_fr_chx_fx latched figure 6.2.2.2.4-1: md_ferr_chx_f1 note that for a special failure condition two error flags for one frame can be set. failure condition: e.g. default ic configuration; psi5 sensor with 189 kbps connected (instead of 125kbps); depending on p si5 data, either 1 or 2 error bits are flagged. frame erro r 111 000 slot counter 001 psi5 data mcd: valid start bit md_ferr_chx_fx md_ no_fr_chx_fx latched n o star t b its d etected in slot ?000 ' latched figure 6.2.2.2.4-2: set of error flags (2errors; da ta=0x3ff) 6.2.3 spi the spi communication between one master and multip le slaves can be operated in parallel or in daisy c hain. parallel operation several spi-slaves can be connected to one spi chan nel. the communication lines sdi_rxd, sdo_txd and c lk are shared and every slave has its own chip select line (ncs). daisy chain operation several slaves can be connected to the c in daisy c hain operation to save c interface pins (one common chip select line for all slaves in the chain). elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 38 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 t hclch t sclcl t cll t clh t sclch t hclcl_an ncs sclk sdo_ txd sdi_ rxd t pcld t scld t hcld t pchdz msb lsb lsb msb spi-ecu12-v3.0.vsd data flow t spi_switch t spi_switch t spi_switch t hclcl_app t csdv t on_ncs t sdo_trans figure 6.2.3-1: data flow graphic in case ncs is high, any signals (e.g. very high cl ock frequencies e.g. 20mhz max.) at the sclk and sd i_rxd pins are ignored, and sdo_txd remains in a high imp edance state. after an ncs high to low transition, the spi response word is multiplexed from the latches that were specified by the last command into the shift r egister, i.e. the sdo_txd changes from high impedance state to th e state of the msb of the last addressed spi regist er, inde- pendent of the spi clock state. the sclk pin must be low when ncs switches to low. at each rising edge of the clock pulse after ncs go es low, the response word is serially shifted out o n the sdo_txd pin. at each falling edge of the clock pulse (after ncs goes low) the new control word is serially shifted in on the sdi_rxd pin. the spi command bits are decoded to de termine the destination address for the data bits. after the 16th (or multiple of 16, for daisy chains) clock cy cle, at the next ncs low to high transition, the sp i shift register data bits are transferred into the latch whose addr ess was decoded from the spi shift register command bits. a command is executed after 16 sclk (or a multiple of 16) and ncs goes high. during reset, sdo_txd is forced into a high impedan ce state and any inputs from sclk and sdi_rxd are ignored. spi format each device is controlled with a 16 bit control com mand, see following chapters. the command is stored in a command register after t he rising edge of ncs. the response consists of a 1 6 bit word which contains the before requested information lik e e.g. diagnostic or output state. response after reset or communication error in case of reset or communication error (not valid commands, number of clocks not multiples of 16) fol lowing response will be sent in the next valid spi frame: "0x0000". the execution of not valid commands is bl ocked and command with ncs low without clock are ignored. order of msb/lsb bit msb is sent first. crc spi packet frames from transceiver to controller in clude a xcrc (see 6.2.5). daisy chain daisy chain operation is supported. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 39 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 6.2.3.1 error handling figure 6.2.3.1-1: spi error handling example 1 1: examples invalid command for 'read sensor data 1 6bit': figure 6.2.3.1-2: spi error handling example 2 4a: example: command 'spi_read_register' including invalid address a[5:0]: figure 6.2.3.1-3: spi error handling example 3 4b: example: command 'spi_read_register' including stuff 0 (frame n): figure 6.2.3.1-4: spi error handling example 4 4c: example: command 'spi_read_register' including stuff 0 (frame n+1): table 6.2.3.1-1: spi communication error 1 invalid commands error_status_1 [uart_spi_inv_cmd] command rejected 2 number of clocks not multiples of 16 error_status_1 [spi_clk_err] command rejected 3a command 'spi_write_register' including invalid address a[5:0] error_status_1 [uart_spi_inv_address] & [uart_spi_inv_cmd] command rejected 3b command 'spi_write_register' including stuff 0 (in frame n+1) no flag frame n+1: correct response frame n+2: wrong xcrc (6bit stuff is used for calculation) elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 40 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 4b command 'spi_read_register' including stuff 0 (in frame n) see #1 command rejected 4c command 'spi_read_register' including stuff 0 (in frame n+1) no flag frame n+1: correct response frame n+2: send zero response including inverted xcrc to uc 5a commands 'spi_get_data_xxb' - not according buffer config- uration e.g. spi_buffer_config="00" and "spi_get_data_16/24/32b" error_status_1 [uart_spi_inv_address] command rejected 5b commands 'spi_get_data_xxb' - according buffer configuration - including invalid chid[2:0] invalid channel identifier chid[2:0]: '000' / '101' / '110' / '111' see #5a command rejected 5c commands 'spi_get_data_ xxb' - according buffer configur- ation - including invalid bid[2:0] invalid buffer identifier bid[2:0] depends on configuration: e.g. spi_buffer_config=0b00 -> '010' / '011' / '100' / '101' / '110' / '111' see #5a command rejected 5d commands 'spi_get_data_ xxb' - including stuff 0 (in frame n) see #1 command rejected 5e commands 'spi_get_data_ xxb' - including stuff 0 (in frame n+1) no flag frame n+1: correct response frame n+2 till before the end of command response: communic- ation error last command response: send zero response including inver- ted xcrc to uc 5f commands 'spi_get_data_ xxb' - including correct spi_sync_pulse cm with 4bit stuff 0 (in frame n+1) see #1 frame n+1: correct response frame n+2 till before the end of command response: communic- ation error last command response: send zero response including inver- ted xcrc to uc 6 command 'spi_sync_pulse' - including stuff 0 (in frame n) see #1 command rejected elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 41 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 9 command 'spi_sw_reset' - including stuff 0 (in frame n) see #1 command rejected 6.2.3.2 overview of communication frames table 6.2.3.2-1: overview of spi communication fram es communication path commands/response s spi frame n [spi packet frame] spi frame n+1 [spi packet frame] spi frame n+2 [spi packet frame] spi frame n+3 [spi packet frame] spi frame n+4 [spi packet frame] c->transceiver spi_nop cmd[3:0]; stuff [11:0] next cmd c->transceiver response response to previous cmd cmd[3 :0]; stuff [11:0] c->transceiver spi_write_register cmd[3:0]; a[5:0]; d[15 :10] d[9:0]; stuff [5:0] spi_write_register spi_read_register spi_sync_pulse spi_nop spi_sw_reset c->transceiver response to spi_write_reg response to previous cmd cmd[3:0]; a[5:0]; d[15:10]; d [9:0]; xcrc[5:0] c->transceiver spi_read_reg cmd[3:0]; a[5:0]; stuff[5:0] st uff[15:0] next cmd c->transceiver response to spi_read_register response to previous cmd cmd[3:0]; a[5:0]; d[15:10] d[ 9:0]; xcrc[5:0] c->transceiver spi_sync_pulse cmd[3:0]; cht[3:0]; chl[3: 0]; stuf f[3:0] next cmd c->transceiver response response to previous cmd cmd[3 :0]; cht[3:0]; chl[3:0]; stuff[3:0] c->transceiver response response to previous cmd cmd[3 :0]; stuff [11:0] c->transceiver spi_get_data_16b cmd[3:0]; chid[2:0]; bid [2:0]; stuff[5:0] stuff[15:0] optional: spi_sync_pulse next cmd c->transceiver response to spi_get_data_16b response to previous cmd cmd[3:0]; chid[2:0]; bid[2:0 ]; stuff[5:0] d[9:0]; xcrc[5:0] c->transceiver sp_get_data_24b cmd[3:0]; chid[2:0]; bid[ 2:0]; stuff[5:0] stuff [15:0] optional: spi_sync_pulse stuff [15:0] next cmd c->transceiver response to spi_get_data_24b response to previous cmd cmd[3:0]; chid[2:0]; bid[2:0 ] fid[2:0]; err[1:0]; d[18] d[17:2] d[1:0]; stuff [7:0]; xcrc[5:0] c->transceiver spi_get_data_32b cmd[3:0]; chid[2:0]; bid [2:0]; stuff [5:0] stuff [15:0] optional: spi_sync_pulse stuff [15:0] next cmd c->transceiver response to spi_get_data_32b response to previous cmd cmd[3:0]; chid[2:0]; bid[2:0 ] fid[2:0]; err[1:0]; d[26] d[25:10] d[9:0]; xcrc[5:0] c->transceiver spi_get_data_48b cmd[3:0]; chid[2:0]; bid [2:0]; stuff [5:0] stuff [15:0] optional: spi_sync_pulse stuff [15:0] stuff [15:0] next cmd c->transceiver response to spi_get_data_48b response to previous cmd cmd[3:0]; chid[2:0]; bid[2:0 ] fid[2:0]; err[1:0]; d[42] d[41:26] d[25:10] d[9:0]; xcrc[5:0] c->transceiver spi_sw_reset cmd[3:0]; stuff [11:0] next cm d c->transceiver response response to previous cmd cmd[3 :0]; stuff [11:0] bid = buffer identifier chid = channel identifier chtx = channel trigger for sync pulse (0=disabled; 1=enabled) elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 42 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 chlx = sync pulse length (0=short; 1=long) note: ? for 'read sensor data xxbit' commands the spi frame n+1 includes optional the 'sync pulse command' instead of nop command to optimize the spi bandwidt h ? the idle time between consecutive spi frames has to fulfill parameter ton_ncs . 6.2.3.3 overview of spi commands all valid spi commands are shown in the table below . any other combinations (commands from micro control ler) are rejected but flagged in register error_status_1[uart_spi_inv_cmd] for diagnosis purp ose. in case of reset or communication error the followi ng response will be sent: 0x0000 in the following v alid spi frame. execution of command is blocked. chip select (ncs) low without any clock pulses at s clk will be ignored. next response to previous vali d frame. table 6.2.3.3-1: overview spi commands spi command command bits[15:12] remaining bits [11:0] spi_write_register 0001 0000 0000 0000 spi_read_register 0010 0000 0000 0000 spi_sync_pulse 0011 0000 0000 0000 spi_get_data_16b 0100 0000 0000 0000 spi_get_data_24b 0101 0000 0000 0000 spi_get_data_32b 0111 0000 0000 0000 spi_get_data_48b 1000 0000 0000 0000 spi_nop 1110 0000 0000 0000 spi_sw_reset 1111 0000 0000 0000 6.2.3.4 no operation command receiving a nop command, the ic will perform no ope ration. it shall be used to get the last frame of a spi com munication sequence. the bit configuration of this one frame command is shown in the figure below: msb lsb msb lsb sdi_rxd idle 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 idle x x x x x x x x x x x x x x x x idle sdo_txd idle x x x x x x x x x x x x x x x x idle 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 idle next cmd response to previous cmd stuff spi_nop spi frame n+1 stuff spi frame n spi_n op figure 6.2.3.4-1: spi nop command 6.2.3.5 write configuration register command with the command "write configuration register" any 16bit register can be written. every command consists of three consecutive spi fra mes, shown in the figure below. as spi frame n+2 on sdi_rxd are following cmds allo wed: spi_write_register, spi_read_register, spi_sync_pulse, spi_nop or a spi_sw_reset. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 43 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 msb lsb msb lsb sdi_rxd idle 0 0 0 1 a5 a4 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 idle d9 d8 d7 d6 d 5 d4 d3 d2 d1 d0 0 0 0 0 0 0 idle msb lsb msb lsb sdo_txd idle x x x x x x x x x x x x x x x x idle 0 0 0 1 a5 a4 a3 a2 a1 a0 d15 d14 d13 d1 2 d11 d10 idle msb lsb sdi_rxd idle x x x x x x x x x x x x x x x x idle msb lsb sdo_txd idle d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x5 x4 x3 x2 x1 x0 idle data stuff spi_write_register address data spi frame n+2 xcrc data response to previous cmd spi_write_register address data spi frame n next cmd spi frame n+1 figure 6.2.3.5-1: spi write register command 6.2.3.6 software reset command with the first execution of the software reset comm and, all configuration registers are initialized to default values if bit asic_cnfg_1[cnfg_lock]='0'. if bit asic_cnfg_1[cnfg_lock]='1' all configuration registers are initialized to default values except register asic_cnfg_1 and asic_cnfg_2. with the second execution of the software reset com mand, the bit asic_cnfg_1[cnfg_lock] is reset to '0 '. the software reset command includes one spi frame o nly: msb lsb msb lsb sdi_rxd idle 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 idle x x x x x x x x x x x x x x x x idle sdo_txd idle x x x x x x x x x x x x x x x x idle 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 idle spi frame n+1 stuff next cmd response to previous cmd stuff spi frame n spi_sw_r eset spi_sw_r eset figure 6.2.3.6-1: spi software reset command 6.2.3.7 read configuration register command with the command "read configuration register" any 16bit register can be read. every command consists of three consecutive spi fra mes. msb lsb msb lsb sdi_rxd idle 0 0 1 0 a5 a4 a3 a2 a1 a0 0 0 0 0 0 0 idle 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 idle sdo_txd idle x x x x x x x x x x x x x x x x idle 0 0 1 0 a5 a4 a3 a2 a1 a0 d15 d14 d13 d1 2 d11 d10 idle msb lsb sdi_rxd idle x x x x x x x x x x x x x x x x idle sdo_txd idle d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x5 x4 x3 x2 x1 x0 idle spi_read_register address data spi frame n+1 stuff spi frame n+2 stuff spi frame n spi_read_register address next cmd data xcrc response to previous cmd figure 6.2.3.7-1: spi read register command 6.2.3.8 sync pulse command sync pulses with different widths can be triggered by sending the sync pulse command. for configuration of the sync pulses there are the two bits chtx and chlx available. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 44 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 bit chtx determines the generation of the sync puls e on the desired channel and chlx determines the wi dth of the pulse, whereas a logical '0' leads to a short and a logical '1' leads to a long sync pulse. the detailed bit setting is shown in the table belo w: table 6.2.3.8-1: sync pulse command spi command command[15:12] sync trigger cht[11:8]+syn c length chlx[7:4] stuffing[3:0] sync pulse 0011 cht3 & cht2 & cht1 & cht0 & chl3 & chl2 & chl1 & chl0 0000 long sync pulse all ch 0011 11111111 0000 long sync pulse ch1 0011 00010001 0000 long sync pulse ch2 0011 00100010 0000 long sync pulse ch3 0011 01000100 0000 long sync pulse ch4 0011 10001000 0000 short sync pulse all ch 0011 11110000 0000 short sync pulse ch1 0011 00010000 0000 short sync pulse ch2 0011 00100000 0000 short sync pulse ch3 0011 01000000 0000 short sync pulse ch4 0011 10000000 0000 example: e.g. '0011 1001 1001 0000' (msb->lsb) defi nes two long sync pulses on channel 1 and channel 4 . note: the application shall ensure to trigger the s ync pulse generator only once during tsync by max. 1 "sync pulse command" per tsync. more trigger commands ove rwrite the former command (if sync pulse delay coun ter has not exceeded) or trigger a new sync pulse. msb lsb msb lsb sdi_rxd idle 0 0 1 1 x x x x x x x x 0 0 0 0 idle x x x x x x x x x x x x x x x x idle cht3 cht2 cht1 cht0 chl3 chl2 chl1 chl0 sdo_txd idle x x x x x x x x x x x x x x x x idle 0 0 1 1 x x x x x x x x 0 0 0 0 idle cht3 cht2 cht1 cht0 chl3 chl2 chl1 chl0 spi frame n spi frame n+1 next cmd response to previous cmd spi_sync_pulse stuff spi_sync_pulse stuff figure 6.2.3.8-1: spi sync pulse command 6.2.3.9 read sensor data sensor data is requested by executing the "read sen sor data" command. the number of spi frames increas es with the number of requested sensor data bits. for example, a request of 16 sensor data bits resul ts in a communication with three spi frames. the spi frame 2 has to be filled with stuffing bits or (optional) it can contain the "sync pulse comma nd" to optim- ize the spi bandwidth by "read sensor data" command . it's mandatory to read block wise via commands spi_ get_data_xxb according the appropriate buffer con- figuration. this means for spi_buffer_config="11" t he command spi_get_data_16b is mandatory (see 6.2.2.1.2 ). for details of the bit position of psi5 parity/crc see 6.2.3.9.1. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 45 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 for synchronous psi5 mode the "spi_data_buffer" has to be synchronized with the psi5 data. it is recommended to read psi5 data buffer after al l psi5 slots within the current cycle where receive d. the spi read access shall start later than "latest psi5-slot end" + 3 t gap and shall end before "earliest psi5-slot end" of the next psi5 slot. t slot 1 psi5 bus voltage psi5 bus current ncs sdi sdo cmd: read_sensor_data slot 1 slot 2 latest end read sensor data command shall not start before latest end + 3 tgap read command shall end before earliest end 3 t gap valid read sensor data window slot n slot 2 earliest end sync spi frame previous response response 1.1 response 1.2 spi frame cmd: read_sensor_data slot n spi frame previous response response n.1 response n.2 spi frame additional sensor data figure 6.2.3.9-1: valid read sensor data window 1 if data buffer has to be read interleaved within th e psi5 cycle the same constrains have to be conside red. the spi read access shall start later than "latest psi5-slot end" + 3 t gap and shall end before "earliest psi5-slot end" of the next psi5 slot. t slot 1 slot n psi5 bus voltage psi5 bus current ncs sdi sdo cmd: read_sensor_data_16b previous cmd response spi frame response 1 spi frame response 2 slot 2 earliest end latest end read sensor data command shall not start before latest end + 3 tgap read command shall end before earliest end 3 t gap valid read sensor data window sync sync figure 6.2.3.9-2: valid read sensor data window 2 for asynchronous sensor mode it is not possible to access the data buffer synchronous to psi5 data. in this case it is recommended to use the uart mode . elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 46 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 6.2.3.9.1 read of 16bit (11bit sensor data) communication template for 16bit (= 3xframeid + 2xe rrbits + 11 databits) is shown in the figure above. note: position of psi5 parity/crc bits in data fram e is represented by highest 'used' data bit dx of s pi buffer. see following examples: ? 10 bit data + 1 parity bit -> d10 = parity bit ? 8 bit data + 1 parity bit -> d8 = parity bit ? 8 bit data + 3 crc bits -> d10=c0, d9=c1, d8=c2 optional to stuff msb lsb msb lsb sdi_rxd idle 0 1 0 0 x x x x x x 0 0 0 0 0 0 idle 0 0 1 1 x x x x x x x x 0 0 0 0 idle chid2 chid1 chid0 bid2 bid1 bid0 cht3 cht2 cht1 cht0 chl3 chl2 chl1 chl0 sdo_txd idle x x x x x x x x x x x x x x x x idle 0 1 0 0 x x x x x x x x x x x d10 idle chid2 chid1 chid0 bid2 bid1 bid0 fid2 fid1 fid0 err1 err0 msb lsb sdi_rxd idle x x x x x x x x x x x x x x x x idle sdo_txd idle d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x5 x4 x3 x2 x1 x0 idle cmd response (copy from read request) spi data buffer spi frame n+2 spi_sync_pulse spi data buffer xcrc next cmd response to previous cmd spi_get_data_16b spi frame n+1 stuff spi frame n spi_get_data_16b stuff figure 6.2.3.9.1-1: spi read sensor data 16bit msb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 lsb 0 cmd3 cmd2 cmd1 cmd0 chid2 chid1 chid0 bid2 bid1 bid0 0 0 1 0 1 0 0 1 1 1 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 identifier buffer4 identifier buffer3 0 0 stuff 0 0 0 0 0 identifier buffer5 spi_get_data_16b; frame1; sdi_rxd identifier ch1 identifier ch2 identifier ch3 identifier ch4 identifier buffer0 0 1 command buffer id channel id 0 identifier buffer1 identifier buffer2 figure 6.2.3.9.1-2: spi read sensor data 16bit-requ est at sdi_rxd -1st spi frame- msb 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 lsb 0 cmd3 cmd2 cmd1 cmd0 chid2 chid1 chid0 bid2 bid1 bid0 fid2 fid1 fid0 err1 err0 d0 data 0 0 1 0 1 0 0 1 1 1 0 0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 0 0 0 1 1 0 1 1 spi_get_data_16b; frame2; sdo_txd x identifier frame4 identifier frame5 identifier frame6 error bit - no error identifier buffer1 identifier buffer2 identifier buffer3 identifier buffer4 identifier buffer5 identifier frame1 identifier ch1 identifier ch2 identifier ch3 identifier ch4 identifier buffer0 error bit - interface error error bit - asic error error bit - interf. + asic error identifier frame3 identifier frame2 buffer id frame id channel id command 0 1 0 0 error bits figure 6.2.3.9.1-3: response to spi read sensor dat a 16bit at sdo_txd -2nd spi frame- elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 47 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 6.2.3.9.2 read of 24bit (19bit sensor data) communication template for 24bit (= 3xframeid + 2xe rrbits + 19 databits): optional to stuff msb lsb msb lsb sdi_rxd idle 0 1 0 1 x x x x x x 0 0 0 0 0 0 idle 0 0 1 1 x x x x x x x x 0 0 0 0 idle chid2 chid1 chid0 bid2 bid1 bid0 cht3 cht2 cht1 cht0 chl3 chl2 chl1 chl0 sdo_txd idle x x x x x x x x x x x x x x x x idle 0 1 0 1 x x x x x x x x x x x d18 idle chid2 chid1 chid0 bid2 bid1 bid0 fid2 fid1 fid0 err1 err0 data msb lsb msb lsb sdi_rxd idle 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 idle x x x x x x x x x x x x x x x x idle sdo_txd idle d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 idle d1 d 0 0 0 0 0 0 0 0 0 x5 x4 x3 x2 x1 x0 idle spi data buffer stuff xcrc spi frame n spi frame n+1 spi_sync_pulse stuff response to previous cmd spi frame n+2 spi frame n+3 stuff next cmd spi data buffer spi_get_data_24b stuff spi_get_data_24b cmd response (copy from read request) spi data buffer figure 6.2.3.9.2-1: read sensor data 24bit command 6.2.3.9.3 read of 32bit (27bit sensor data) communication template for 32bit (= 3xframeid + 2xe rrbits + 27 databits): optional to stuff msb lsb msb lsb sdi_rxd idle 0 1 1 1 x x x x x x 0 0 0 0 0 0 idle 0 0 1 1 x x x x x x x x 0 0 0 0 idle chid2 chid1 chid0 bid2 bid1 bid0 cht3 cht2 cht1 cht0 chl3 chl2 chl1 chl0 sdo_txd idle x x x x x x x x x x x x x x x x idle 0 1 1 1 x x x x x x x x x x x d26 idle chid2 chid1 chid0 bid2 bid1 bid0 fid2 fid1 fid0 err1 err0 data msb lsb msb lsb sdi_rxd idle 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 idle x x x x x x x x x x x x x x x x idle sdo_txd idle d25 d24 d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 d11 d1 0 idle d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 x5 x4 x3 x2 x1 x0 idle stuff spi_get_data_32b xcrc spi data buffer spi frame n spi frame n+1 spi_sync_pulse stuff response to previous cmd spi frame n+2 spi frame n+3 stuff next cmd spi data buffer spi_get_data_32b cmd response (copy from read request) spi data buffer figure 6.2.3.9.3-1: read sensor data 32bit command 6.2.3.9.4 read of 48bit (43bit sensor data) position of psi5 parity/crc bits -> see 'read senso r data 16bit' communication template for 48bit (= 3xframeid + 2xe rrbits + 43 databits): figure 6.2.3.9.4-1: read sensor data 48bit command note: for bits 'don't care' in frame n+1 / n+2 on s do_txd there are two scenarios: all 12 bits are eit her '0' or '1'; for more details see chapter 6.2.2.1.2. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 48 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 6.2.4 uart the uart data rate is derived from an external cloc k signal f sclk_uart with dc sclk_uart at pin sclk and is calculated with the following formula f uart = . the external clock has to be supplied permanent. the bit shift direction supports "little endian" fo rmat with lsb sent first. 6.2.4.1 error handling sdi_rxd frame1: chid / cmd sdo_txd frame2: address / stuff read register command invalid address frame1: chid / fid / err frame2: copy from read request response to read register command frame3: d[7:0] = 0x00 frame4: d[15:8] = 0x00 frame5: stuff / xcrc m odified data figure 6.2.4.1-1: uart error handling example 1 see #3: command 'uart_read_register' including inva lid address a[5:0]: the 'response to read register command' is uploaded with with data bits d[15:0] = 0x0000. sdi_rxd frame1 sdo_txd frame2 read register command n o collision; read reg .cmd decoded after response finished frame1 frame2 response to read register command frame3 frame4 frame5 frame1 frame2 read register command sdi_rxd frame1 sdo_txd frame2 read register command frame1 frame2 response to read register command frame3 frame4 frame5 frame1 frame2 read register command collision; read reg .cmd decoded before response finished frame1 frame2 figure 6.2.4.1-2: uart error handling example 2 see #6: collision of 'uart_read_register' commands: while read register request command a collision wit h frames sent by the transceiver might occur. in case of frames sent to the transceiver at pin rx d while the transceiver is transmitting data on pin txd the rxd frame is ignored. to ensure a response from e521.4x device to a "read register cmd", the sdo_txd has t o be idle during decoding of "read register cmd". this i s feasible if "transfer of psi5 data" is predictabl e. for systems with asynchronous sensors it is recomme nded to use only one asynchronous sensor per chip. the probability of a response to "read register cmd" in creases with decreased payload on sdo_txd. the prob ability of a response to "read register cmd" increases with increased uart baud rate. to decrease payload the uart idle time can be incre ased by register asic_cnfg_2 / uart_idle_time[3:0] set to maximum value. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 49 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 if synchronous mode is used the uart idle time can be predicted. example for uart =4mbaud: ? t1 = tnee (earliest end of frame) = 142us ? t2 3 x staggering + 1 uart frame = 3*10us + 55bit* 0.25us = 44us => idle time = t1 + t2 = 98us figure 6.2.4.1-3: syncpulse staggering table 6.2.4.1-1: uart error handling 1 invalid commands error_status_1 [uart_spi_inv_cmd] command rejected 2a command 'uart_write_register' includ- ing invalid address a[5:0] error_status_1 [uart_spi_inv_address] command rejected 2b command 'uart_write_register' includ- ing chid 0 error_status_1 [uart_spi_inv_cmd] command rejected 2c command 'uart_write_register' includ- ing stuff 0 error_status_1 [uart_spi_inv_address] command rejected 3a command 'uart_read_register' includ- ing invalid address a[5:0] error_status_1 [uart_spi_inv_address] command rejected 3b command 'uart_read_register' includ- ing chid 0 error_status_1 [uart_spi_inv_cmd] command rejected elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 50 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 3c command 'uart_read_register' includ- ing stuff 0 error_status_1 [uart_spi_inv_address] command rejected 4 wrong parity bit received error_status_1 [uart_perr] command rejected 5 frame error = invalid stop bit error_status_1 [uart_ferr] command rejected 6 collision of 'uart_read_register' com- mands e.g. read request received while last read was not completed yet error_status_1 [uart_spi_collision] 2nd command rejected 7 command 'short sync pulse' including chid >4 error_status_1 [uart_spi_inv_cmd] command rejected 8 command 'long sync pulse' including chid >4 error_status_1 [uart_spi_inv_cmd] command rejected 9 command 'no sync pulse' including chid 0 error_status_1 [uart_spi_inv_cmd] command rejected 11 command 'sw reset' including chid 0 error_status_1 [uart_spi_inv_cmd] command rejected 6.2.4.2 packet frame definition a frame on the psi5 interface is represented by a p acket frame on the transmission line from the trans ceiver to the controller. also the commands on the transmission line from the controller to the transceiver asic, as well as the responses, are represented by a packet frame. a packet frame can be a concatenation of 1 to 6 uar t frames. for asic->uc: an idle time from 1 to 16 idle bits ( configurable in register asic_cnfg_2) is implemente d between consecutive packet frames from the uart in order to enable a re-synchronization of the next packet fra me. the uart frame following an idle time which is equal or greater than the minimum idle time thus is always be assumed as the header of the next packet frame (default con figuration: one bit minimum idle time between two p acket frames). for uc->asic: frames can be sent w/o idle time (bac k-to-back transfer possible) 6.2.4.3 uart frame definition for transceiver to c communication a uart frame (in side a packet frame) is composed of 1 start bit, 8 data bits, optional parity bit and 1 stop bit. for c to transceiver communication a uart frame (in side a packet frame) is composed of 1 start bit, 8 data bits, 1 parity bit and 1 stop bit. odd parity is enabled by default. for transceiver t o c communication the usage of a parity bit is conf igurable. there is no idle time between uart frames inside a packet frame (i.e. a stop bit of a uart frame is fo llowed by the start bit of a potentially following uart frame without any gap). elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 51 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 communication path idle (h) start (l) d0 d1 d2 d3 d4 d5 d6 d7 p (odd) stop (h) idle (h) lsb msb t idle (h) start (l) d0 d1 d2 d3 d4 d5 d6 d7 stop (h) idle (h) lsb msb idle (h) start (l) d0 d1 d2 d3 d4 d5 d6 d7 p (odd) stop (h) idle (h) lsb msb t data transmission transceiver -> c c -> transceiver uart frame uart frame (config1) uart frame (config2) figure 6.2.4.3-1: uart data transmission 6.2.4.4 overview of communication frames the defined uart commands and responses, with numbe r of uart frames per packet frame, are shown in the table below. ? packet frames from c to transceiver means downstrea m ? packet frames from transceiver to c means upstream table 6.2.4.4-1: overview of communication frames communication path commands/responses uart frame 1 [packet- frame1] uart frame 2 [packetframe1] uart frame 3 [packetframe1] uart frame 4 [packetframe1] uart frame 5 [pack- etframe1] uart frame 6 [packetframe1] c -> transceiver uart_write_register cmd[4:0], chid[2 :0] stuff[1:0], a[5:0] d[7:0] d[15:8] c -> transceiver uart_read_register cmd[4:0], chid[2: 0] stuff[1:0], a[5:0] c -> transceiver uart_short_sync_pulse cmd[4:0], chid[2 :0] c -> transceiver uart_long_sync pulse cmd[4:0], chid[2 :0] c -> transceiver uart_no_sync_pulse cmd[4:0], chid[2:0] c -> transceiver uart_software_reset cmd[4:0], chid[2: 0] transceiver -> c response to read register err[1:0], fid[2:0], chid[2 :0] cmdres[7:0] d[7:0] d[15:8] xcrc[5:0], stuff[1:0] transceiver -> c upload psi5 data err[1:0], fid[2:0], chid[2:0] d[7:0] x * x * x * x * note: x * = depending on definition of the corresponding psi 5 frame 6.2.4.5 overview of uart commands all valid uart commands are shown in the table belo w. these commands have a hamming distance 2 to each other. any other command from controller is rejecte d but flagged in register error_status_1[uart_spi_inv_cmd] for diagnosis purp ose. table 6.2.4.5-1: uart command table uart command command[7:3] channel id[2:0] uart_write_register 00001 000 uart_read_register 00010 000 elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 52 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 uart command command[7:3] channel id[2:0] uart_short_sync_pulse all ch 00100 000 uart_short_sync_pulse ch1 00100 001 uart_short_sync_pulse ch2 00100 010 uart_short_sync_pulse ch3 00100 011 uart_short_sync_pulse ch4 00100 100 uart_long_sync_pulse all ch 00111 000 uart_long_sync_pulse ch1 00111 001 uart_long_sync_pulse ch2 00111 010 uart_long_sync_pulse ch3 00111 011 uart_long_sync_pulse ch4 00111 100 uart_no_sync_pulse 10011 000 uart_software_reset 10101 000 6.2.4.6 write register command the write register sequence includes 4 uart frames: uart frame 1: command bits cmd[4:0]; channel identi fier chid[2:0] uart frame 2: stuffing bits[1:0], address bits a[5: 0] uart frame 3: data low byte d[7:0] uart frame 4: data low byte d[15:8] table 6.2.4.6-1: write register command write register command command [7:3] channel id [2:0] write register command 00001 000 srt 0 0 0 1 0 0 0 0 parity stp srt a0 a1 a2 a3 a4 a5 0 0 parity stp srt d0 d1 d2 d3 d4 d5 d6 d7 parity stp c h id 0 c h id 1 c h id 2 c m d 0 c m d 1 c m d 2 c m d 3 c m d 4 stuff stuff srt d8 d9 d10 d11 d12 d13 d14 d15 parity stp idle uart_write_register uart frame 3 data lo-byte uart frame 4 uart frame 1 uart frame 2 address data hi-byte figure 6.2.4.6-1: write register command packet fra me 6.2.4.7 read register command the read register sequence includes 2 uart frames: uart frame 1: command bits cmd[4:0]; channel identi fier chid[2:0] uart frame 2: stuffing bits[1:0], address bits a[5: 0] table 6.2.4.7-1: read register command read register command command [7:3] channel id [2:0] read register command 00010 000 srt 0 0 0 0 1 0 0 0 parity stp srt a0 a1 a2 a3 a4 a5 0 0 parity stp idle c h id 0 c h id 1 c h id 2 c m d 0 c m d 1 c m d 2 c m d 3 c m d 4 stuff stuff uart_read_register uart frame 1 uart frame 2 address figure 6.2.4.7-1: read register command packet fram e elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 53 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 6.2.4.8 short sync pulse command the short sync pulse command includes 1 uart frame only: uart frame 1: command bits cmd[4:0]; channel identi fier chid[2:0] following table shows the configuration of channel ids: table 6.2.4.8-1: short sync pulse command short sync pulse command command [7:3] channel id [2: 0] short sync pulse all ch 00100 000 short sync pulse ch1 00100 001 short sync pulse ch2 00100 010 short sync pulse ch3 00100 011 short sync pulse ch4 00100 100 srt x x x 0 0 1 0 0 parity stp idle c h id 0 c h id 1 c h id 2 c m d 0 c m d 1 c m d 2 c m d 3 c m d 4 uart_short_sync_pulse uart frame figure 6.2.4.8-1: short sync command packet frame 6.2.4.9 long sync pulse command the long sync pulse command includes 1 uart frame o nly: uart frame 1: command bits cmd[4:0]; channel identi fier chid[2:0] following table shows the configuration of channel ids: table 6.2.4.9-1: long sync pulse command long sync pulse command command [7:3] channel id [2:0 ] long sync pulse all ch 00111 000 long sync pulse ch1 00111 001 long sync pulse ch2 00111 010 long sync pulse ch3 00111 011 long sync pulse ch4 00111 100 srt x x x 1 1 1 0 0 parity stp idle c h id 0 c h id 1 c h id 2 c m d 0 c m d 1 c m d 2 c m d 3 c m d 4 uart frame uart_long_sync_pulse figure 6.2.4.9-1: long sync command packet frame 6.2.4.10 no sync pulse command for the tooth gap method, if a logical '0' (=absenc e of sync pulse) for ecu to sensor communication is required, a no sync pulse command can be send by the controll er. the no sync pulse command includes 1 uart frame onl y. uart frame 1: command bits cmd[4:0]; channel identi fier chid[2:0] elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 54 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 table 6.2.4.10-1: no sync pulse command no sync pulse command command [7:3] channel id [2:0] no sync pulse 10011 000 srt 0 0 0 1 1 0 0 1 parity stp idle c h id 0 c h id 1 c h id 2 c m d 0 c m d 1 c m d 2 c m d 3 c m d 4 uart_no_sync_pulse uart frame figure 6.2.4.10-1: no sync pulse command packet fra me 6.2.4.11 software reset command with the first execution of the software reset comm and, all configuration registers are initialized to default values if bit asic_cnfg_1[cnfg_lock]='0'. if bit asic_cnfg_1[cnfg_lock]='1' all configuration registers are initialized to default values except register asic_cnfg_1 and asic_cnfg_2. with the second execution of the software reset com mand, the bit asic_cnfg_1[cnfg_lock] is reset to '0 '. the software reset command includes 1 uart frame on ly: uart frame 1: command bits cmd[4:0]; channel identi fier chid[2:0] table 6.2.4.11-1: software reset command software reset command command [7:3] channel id [2:0] software reset 10101 000 srt 0 0 0 1 0 1 0 1 parity stp idle c h id 0 c h id 1 c h id 2 c m d 0 c m d 1 c m d 2 c m d 3 c m d 4 uart_sw_reset uart frame figure 6.2.4.11-1: software reset command frame 6.2.4.12 response to read register command each valid read command, received by the transceive r asic, results in a response sequence including 5 uart frames. uart frame 1: channel identifier chid[2:0]; frame i dentifier fid[2:0]; error bits err[1:0] uart frame 2: command response cmdres[4:0]; channel identifier[2:0]= copy from uart frame 1 of read request uart frame 3: data low byte d[7:0] uart frame 4: data low byte d[15:8] uart frame 5: stuffing bits stuff[1:0]; 6bit checks um xcrc[5:0] following table shows the bit configuration of uart frame 1 including chid, fid and err bits. table 6.2.4.12-1: response to read command bit conf iguration response to read register: configura- tion of uart frame 1 error bits[7:6] frame id[5:3] channel id[2:0] error bit - no asic error 00 000 000 error bit - interface error 01 000 000 error bit - asic error 10 000 000 error bit - asic and interface error 11 000 000 elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 55 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 idle srt 0 0 0 0 0 0 0 err1 stp srt 0 0 0 0 1 0 0 0 stp srt d0 d1 d2 d3 d4 d5 d6 d7 s tp c h id 0 c h id 1 c h id 2 f id 0 f i d 1 f id 2 e r r 0 c h id 0 c h id 1 c h id 2 c m d 0 c m d 1 c m d 2 c m d 3 c m d 4 srt d8 d9 d10 d11 d12 d13 d14 d15 stp srt 0 0 x0 x1 x2 x3 x4 x5 stp idl e stuff stuff uart frame 4 uart frame 5 data hi-byte xcrc uart frame 1 uart frame 2 uart frame 3 packet frame header cmd response (copy from read request) data lo-byte figure 6.2.4.12-1: response to read register comman d packet frame 6.2.4.13 transfer psi5 data incoming psi5 data frames are processed and transmi tted to the controller in uart frames. the sequence includes 3 - 6 uart frames, depending on the length of the corresponding psi5 frame. example: frame configuration for minimum packet fra me (according to v1.3): uart frame 1: channel identifier chid[2:0]; frame i dentifier fid[2:0]; error bits err[1:0] uart frame 2: data bits d[7:0] uart frame 3: parity; stuffing bit stuff; 6bit chec ksum xcrc[5:0] idle srt chid0 chid1 chid2 fid0 fid1 fid2 err0 err1 stp srt d0 d1 d2 d 3 d4 d5 d6 d7 stp srt parity 0 x0 x1 x2 x3 x4 x5 stp idle stuff xcrc uart frame 3 packet frame header psi5 message uart frame 1 uart frame 2 figure 6.2.4.13-1: example: upload psi5 data minimu m packet frame example: frame configuration for maximum packet fra me (according to v2.0): uart frame 1: channel identifier chid[2:0]; frame i dentifier fid[2:0]; error bits err[1:0] uart frame 2: data bits d[7:0] uart frame 3: data bits d[15:8] uart frame 4: data bits d[23:16] uart frame 5: data bits d[27:24]; 3bit checksum c[2 :0]; stuffing bit stuff uart frame 6: stuffing bits stuff[1:0]; 6bit checks um xcrc[5:0] idle srt chid0 chid1 chid2 fid0 fid1 fid2 err0 err1 stp srt d0 d1 d2 d 3 d4 d5 d6 d7 stp srt d8 d9 d10 d11 d12 d13 d14 d15 stp srt d16 d17 d18 d19 d20 d21 d22 d23 stp srt d24 d25 d26 d27 c2 c1 c0 0 stp srt 0 0 x0 x1 x2 x3 x4 x5 stp idle stuff stuff stuff uart frame 6 packet frame header psi5 message xcrc psi5 message uart frame 4 uart frame 5 psi5 message psi5 message uart frame 3 uart frame 1 uart frame 2 figure 6.2.4.13-2: example: upload psi5 data maximu m packet frame elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 56 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 following table shows the bit configuration of uart frame 1 including chid, fid and err bits. table 6.2.4.13-1: psi5 data uart frame1 bit configu ration psi5 data: configuration of uart frame 1 error bits f rame id channel id identifier for channel0 (diagnosis) xx xxx 000 identifier for channel1 xx xxx 001 identifier for channel2 xx xxx 010 identifier for channel3 xx xxx 011 identifier for channel4 xx xxx 100 identifier for frame1 xx 000 xxx identifier for frame2 xx 001 xxx identifier for frame3 xx 010 xxx identifier for frame4 xx 011 xxx identifier for frame5 xx 100 xxx identifier for frame6 xx 101 xxx error bit - no error 00 xxx xxx error bit - interface error 01 xxx xxx error bit - asic error 10 xxx xxx error bit - interface + asic error 11 xxx xxx 6.2.5 xcrc[5:0] calculation a 6-bit xcrc for error detection is calculated and added at the last uart/spi frame, transferred from transceiver to c at pin sdo_txd, for the defined packet frames. the generator polynomial of the six bit crc is g(x) = + + + 1 with a binary crc initialization value "0 10101". the transmitter extends the data bits by six zeros (= xcrc default condition) as shown in the figures above. this augmented data word is fed (lsb first) into the shi ft registers of the crc generator. t t t t t t input data 1*1 + + + + + + 0*x 0*x 2 1*x 3 1*x 4 0*x 5 1*x 6 = 1 + x 3 + x 4 + x 6 c0 c1 c2 c3 c4 c5 figure 6.2.5-1: xcrc-calculation for spi frames uart packet frames : the sequence of bit shift into the register for the crc calculation is shown in below, starting with l sb first. the number of stuffing bits varies with the payload (no t shown in the figures below). 1. transfer psi5 data lsb msb x x x x x x x x x x x x x x x x x 0 0 0 x x x x x x d0 d1 d2 ?? dn-2 dn-1 c2 c1 c0 ?. x0 x5 channel id frame id error bits psi5 frame data p/crc xcr c; default = zeros stuffing figure 6.2.5-2: xcrc: example transfer psi5 data elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 57 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 2. response to read register command lsb msb 0 0 0 0 0 0 0 x 0 0 0 0 1 0 0 0 x x x x x x 0 0 x x x x x x d0 d1 d2 ?? d14 d15 x0 x5 xcrc; default = zeros stuffing channel id frame id error bits cmd response (copy from read request) channel id cmd register data figure 6.2.5-3: xcrc: example response to read comm and spi packet frames : the sequence is done in the similar way than for ua rt packet frames, except ? starting with msb first ? changed payload (e.g. additional buffer id, sync_lo ng bits) example read sensor data 24bit : lsb msb 0 0 0 0 0 0 0 x 0 0 0 0 1 0 0 0 x x x x x x 0 0 x x x x x x d0 d1 d2 ?? d14 d15 x0 x5 xcrc; default = zeros stuffing channel id frame id error bits cmd response (copy from read request) channel id cmd register data figure 6.2.5-4: xcrc example read sensor data 24bit 6.2.6 configuration 6.2.6.1 asic configuration the device can be configured and maintained with co nfiguration, diagnosis and error registers. every register contains 16 bits, so only 16 bit rea d/write requests are processed. any of the four device channels can be configured i ndependently by writing the read/write (r/w) config uration registers asic_cnfg_1, asic_cnfg_2 and asic_cnfg_3. the following parameters can be modified per channe l: ? current threshold for the data comparator ( is_chx) ? sync sustain voltage v3 (vsync_v3_chx) ? channel configuration of synchronous / asynchronous mode (async_chx) ? psi5 bit time [kbps] / baud rate per channel (psi5_ bit_time_chx) ? enabling of interfaces sif_chx (en_chx) the detailed settings are described in the register table below: table 6.2.6.1-1: asic configuration register name address description asic_cnfg_1 0x00 asic configuration register 1 asic_cnfg_2 0x01 asic configuration register 2 asic_cnfg_3 0x02 asic configuration register 3 reading of unused bits will always return '0' and w riting of unused bits don't care. writing of read-o nly- or read-on clear-registers, don't care. for spi accesses the r esponse via sdo_txd is the echo of the write reques t (identic- ally behaviour than for write on read/write-registe rs). elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 58 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 table 6.2.6.1-2: register asic_cnfg_1 (0x00) asic configuration register 1 msb lsb content cnfg _loc k - - - mcd_data_ cmp_w[1:0] vsyn c_v3 _ch4 vsyn c_v3 _ch3 vsyn c_v3 _ch2 vsyn c_v3 _ch1 is_c h4 is_c h3 is_c h2 is_c h1 v_bus[1:0] reset value 0 0 0 0 00 0 0 0 0 0 0 0 0 00 access r/w r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description cnfg_lock : lock bit for configuration registers 0b0: registers asic_cnfg_1 and asic_cnfg_2 are not locked, an update is possible 0b1: registers asic_cnfg_1 and asic_cnfg_2 are lock ed, no update possible (exception: the 2nd sw_reset com- mand resets the lock and allows this two registers to be updated) mcd_data_cmp_w[1:0] : manchester data compare window setting 0b00: data_edge = 18 clock counts (low sensitive) & compensation_window = 23 clock counts @4mhz: data_e=(18*250ns = 4.5us; cmp=23*250ns=5.75u s; => total=10.25us @6mhz: data_e=18*167ns = 3us; cmp=23*167ns=3.83us; => total = 6.83us 0b01: data_edge = 12 clock counts (low sensitive) & compensation_window = 26 clock counts @4mhz: data_e=12*250ns = 3us; cmp=26*250ns=6.5us; = > total=9.5us @6mhz: data_e=12*167ns = 2us; cmp=26*167ns=4.33us; => total = 6.33us 0b10: data_edge = 8 clock counts (low sensitive) & compensation_window = 28 clock counts @4mhz: data_e=8*250ns = 2us; cmp=28*250ns=7us; => t otal=9us @6mhz: data_e=8*167ns = 1.33us; cmp=28*167ns=4.67us ; => total = 6us vsync_v3_ch4 : sync sustain voltage v3 (vsync_v3_chx) 0b0: v3 = 4.8v typical (common mode) 0b1: v3 = 3.7v typical (low power mode) vsync_v3_ch3 : sync sustain voltage v3 (vsync_v3_chx) 0b0: v3 = 4.8v typical (common mode) 0b1: v3 = 3.7v typical (low power mode) vsync_v3_ch2 : sync sustain voltage v3 (vsync_v3_chx) 0b0: v3 = 4.8v typical (common mode) 0b1: v3 = 3.7v typical (low power mode) vsync_v3_ch1 : sync sustain voltage v3 (vsync_v3_chx) 0b0: v3 = 4.8v typical (common mode) 0b1: v3 = 3.7v typical (low power mode) ? is_ch4 : current threshold for the data comparator ( is_ch x) 0b0: is = 26ma 0b1: is = 13ma ? is_ch3 : current threshold for the data comparator ( is_ch x) 0b0: is = 26ma 0b1: is = 13ma ? is_ch2 : current threshold for the data comparator ( is_ch x) 0b0: is = 26ma 0b1: is = 13ma ? is_ch1 : current threshold for the data comparator ( is_ch x) 0b0: is = 26ma 0b1: is = 13ma v_bus[1:0] : v bus selection 0b00: ldo disabled; v bus must be supplied externaly 0b01: vbus = 5.15v 0b10: vbus = 6.65v 0b11: vbus = 7.7v elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 59 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 table 6.2.6.1-3: register asic_cnfg_2 (0x01) asic configuration register 2 msb lsb content - - uart_idle_time[3:0] rev_ cur_ ch_di s idac_ res psi5_ bit_ti me_c h4 psi5_ bit_ti me_c h3 psi5_ bit_ti me_c h2 psi5_ bit_ti me_c h1 asyn c_ch 4 asyn c_ch 3 asyn c_ch 2 asyn c_ch 1 reset value 0 0 0000 0 0 0 0 0 0 0 0 0 0 access r r r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description uart_idle_time[3:0] : uart idle time between two consecutive uart pack et frames (to enable a re-synchronization) 0b0000: minimum idle time = default 0b1111: maximum idle time rev_cur_ch_dis : disable of channels for reverse current conditio n 0b0: disabled -> no switch-off of channels by ic (d efault) 0b1: enabled -> switch-off dedicated channel if rev _cur_chx='1' idac_res : idac resolution 0b0: 300 ua per lsb (default) 0b1: 200 ua per lsb psi5_bit_time_ch4 : psi5 bit time 0b0: bit time equal to 8us (=125kbps) 0b1: bit time equal to 5.3us (=189kbps) psi5_bit_time_ch3 : psi5 bit time 0b0: bit time equal to 8us (=125kbps) 0b1: bit time equal to 5.3us (=189kbps) psi5_bit_time_ch2 : psi5 bit time 0b0: bit time equal to 8us (=125kbps) 0b1: bit time equal to 5.3us (=189kbps) psi5_bit_time_ch1 : psi5 bit time 0b0: bit time equal to 8us (=125kbps) 0b1: bit time equal to 5.3us (=189kbps) async_ch4 : channel mode configuration 0b0: channel in synchronous configuration 0b1: channel in asynchronous configuration async_ch3 : channel mode configuration 0b0: channel in synchronous configuration 0b1: channel in asynchronous configuration async_ch2 : channel mode configuration 0b0: channel in synchronous configuration 0b1: channel in asynchronous configuration async_ch1 : channel mode configuration 0b0: channel in synchronous configuration 0b1: channel in asynchronous configuration elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 60 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 table 6.2.6.1-4: register asic_cnfg_3 (0x02) asic configuration register 3 msb lsb content - bl_c han- nel4 bl_c han- nel3 bl_c han- nel2 bl_c han- nel1 gen_ fuse _rd en_loop[2:0] en_c p_sy nc en_u art_ txd_ par- ity en_u art_ rxd_ par- ity en_c h4 en_c h3 en_c h2 en_c h1 reset value 0 0 0 0 0 0 000 0 1 0 0 0 0 0 access r r r r r r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description bl_channel4 : blanking time of mcd/sync generation/ovc after c hannel enable 0=5ms 1=10ms bl_channel3 : blanking time of mcd/sync generation/ovc after c hannel enable 0=5ms 1=10ms bl_channel2 : blanking time of mcd/sync generation/ovc after c hannel enable 0=5ms 1=10ms bl_channel1 : blanking time of mcd/sync generation/ovc after c hannel enable 0=5ms 1=10ms gen_fuse_rd : start fuse read out via uart/spi 0b0: no fuse read out 0b1: start additional fuse read out en_loop[2:0] : enable channel in loop back test mode 0b000: all channel in normal operation 0b001: channel1 loop back test mode enabled 0b010: channel2 loop back test mode enabled 0b011: channel3 loop back test mode enabled 0b100: channel4 loop back test mode enabled en_cp_sync : enable sync pulse charge pump 0b0:disabled 0b1:enabled en_uart_txd_parity : enable parity bit addition for uart tx frames 0b0:disabled 0b1:enabled en_uart_rxd_parity : enable parity check for uart received frames 0b0:disabled 0b1:enabled en_ch4 : enable interface sifx 0b0: disable psi5 interface 0b1: enable psi5 interface en_ch3 : enable interface sifx 0b0: disable psi5 interface 0b1: enable psi5 interface en_ch2 : enable interface sifx 0b0: disable psi5 interface 0b1: enable psi5 interface en_ch1 : enable interface sifx 0b0: disable psi5 interface 0b1: enable psi5 interface elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 61 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 6.2.6.1.1 asynchronous mode note: only one sensor allowed per sifx. with enable of sifx via configuration register asic _cnfg_3[en_chx], the sensor is supplied with voltag e vsifx and starts to transmit psi5 sensor frames. for received frames, the implemented manchester dec oder adds to each valid frame the fid ="0b001". for uart interface, the packet frame is transferred to uc automatically. with appropriate uart baud ra te, the ic transmits the data to the uc without any overwritin g. for spi interface, the decoded frame is available i n bid[0] of spi data buffer. the uc has to ensure t o read bid[0] before a new psi5 frame is decoded; otherwise it's overwritten. 6.2.6.2 timeslot configuration for every channel there are seven configuration reg isters available to configure the following paramet ers: ? six independent configurable psi5 timeslots ? timeslot length ? frame length ? parity or crc selection ? error check enabling ? desired delay of sync pulse generation ? mandatory buffer for spi access details are describ ed in the following register table. table 6.2.6.2-1: channel_configuration register name address description ch1_cfg1 0x03 channel 1 configuration register 1 ch1_cfg2 0x04 channel 1 configuration register 2 ch1_cfg3 0x05 channel 1 configuration register 3 ch1_cfg4 0x06 channel 1 configuration register 4 ch1_cfg5 0x07 channel 1 configuration register 5 ch1_cfg6 0x08 channel 1 configuration register 6 ch1_cfg7 0x09 channel 1 configuration register 7 ch2_cfg1 0x0a channel 2 configuration register 1 ch2_cfg2 0x0b channel 2 configuration register 2 ch2_cfg3 0x0c channel 2 configuration register 3 ch2_cfg4 0x0d channel 2 configuration register 4 ch2_cfg5 0x0e channel 2 configuration register 5 ch2_cfg6 0x0f channel 2 configuration register 6 ch2_cfg7 0x10 channel 2 configuration register 7 ch3_cfg1 0x11 channel 3 configuration register 1 ch3_cfg2 0x12 channel 3 configuration register 2 ch3_cfg3 0x13 channel 3 configuration register 3 ch3_cfg4 0x14 channel 3 configuration register 4 ch3_cfg5 0x15 channel 3 configuration register 5 ch3_cfg6 0x16 channel 3 configuration register 6 ch3_cfg7 0x17 channel 3 configuration register 7 elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 62 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 register name address description ch4_cfg1 0x18 channel 4 configuration register 1 ch4_cfg2 0x19 channel 4 configuration register 2 ch4_cfg3 0x1a channel 4 configuration register 3 ch4_cfg4 0x1b channel 4 configuration register 4 ch4_cfg5 0x1c channel 4 configuration register 5 ch4_cfg6 0x1d channel 4 configuration register 6 ch4_cfg7 0x1e channel 4 configuration register 7 it is highly recommended, not to change the registe rs chx_cfg1(idac_cnt_mode, idac_cnt_inc2[1:0], idac_cnt_inc1[1:0]) and chx_cfg2(idac_cnt_dec2[1:0] , idac_cnt_dec1[1:0]) since these registers control the ibase tracking function! table 6.2.6.2-2: register ch1_cfg1 (0x03) channel 1 configuration register 1 msb lsb content idac_ cnt_ mode idac_cnt_i nc2[1:0] idac_cnt_i nc1[1:0] en_e r_ch k t1_c rc ts1_flen[4:0] t1_len[3:0] reset value 0 00 00 0 0 00011 0100 access r/w r/w r/w r/w r/w r/w r/w bit description idac_cnt_mode : reserved idac_cnt_inc2[1:0] : reserved idac_cnt_inc1[1:0] : reserved en_er_chk : enable parity/crc check functionality 0b0: disable functionality 0b1: enable functionality t1_crc : psi5 frame error detection mode of frames starti ng in timeslot 1 0b0: psi5 sensor in parity mode 0b1: psi5 sensor in crc mode ts1_flen[4:0] : psi5 frame length of frames starting in timeslot 1 frame length includes start bit + data + parity/crc [tsx_flen] 16 = [frame length] 10 - [10] 10 0x0 = bit length of zero (=no frame) 0x01 - 0x17: frame length => [11..33] 0x18 - 0x1f: reserved default: p10p (airbag) = 2 + 10 + 1 = 13->0x3 t1_len[3:0] : timeslot 1 length 0b_nnnn: nnnn x 32 us => [0us..480us] default: t = 4*32us = 128us elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 63 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 table 6.2.6.2-3: register ch1_cfg2 (0x04) channel 1 configuration register 2 msb lsb content - idac_cnt_d ec2[1:0] idac_cnt_d ec1[1:0] en_e r_ch k t2_c rc ts2_flen[4:0] t2_len[3:0] reset value 0 01 01 0 0 00011 0101 access r/w r/w r/w r/w r/w r/w r/w bit description idac_cnt_dec2[1:0] : reserved idac_cnt_dec1[1:0] : reserved en_er_chk : enable parity/crc check functionality 0b0: disable functionality 0b1: enable functionality t2_crc : psi5 frame error detection mode of frames starti ng in timeslot 2 0b0: psi5 sensor in parity mode 0b1: psi5 sensor in crc mode ts2_flen[4:0] : psi5 frame length of frames starting in timeslot 2 frame length includes start bit + data + parity/crc [tsx_flen] 16 = [frame length] 10 - [10] 10 0x0 = bit length of zero (=no frame) 0x01 - 0x17: frame length => [11..33] 0x18-0x1f:res erved default: p10p (airbag) = 2 + 10 + 1 = 13->0x3 t2_len[3:0] : timeslot 2 length 0b_nnnn: nnnn x 32 us => [0us..480us] default: t = 5*32us = 160us table 6.2.6.2-4: register ch1_cfg3 (0x05) channel 1 configuration register 3 msb lsb content - - - - - en_e r_ch k t3_c rc ts3_flen[4:0] t3_len[3:0] reset value 0 0 0 0 0 0 0 00011 0101 access r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description en_er_chk : enable parity/crc check functionality 0b0: disable functionality 0b1: enable functionality t3_crc : psi5 frame error detection mode of frames starti ng in timeslot 3 0b0: psi5 sensor in parity mode 0b1: psi5 sensor in crc mode ts3_flen[4:0] : psi5 frame length of frames starting in timeslot 3 frame length includes start bit + data + parity/crc [tsx_flen] 16 = [frame length] 10 - [10] 10 0x0 = bit length of zero (=no frame) 0x01 - 0x17: frame length => [11..33] 0x18 - 0x1f: reserved default: p10p (airbag) = 2 + 10 + 1 = 13->0x3 t3_len[3:0] : timeslot 3 length 0b_nnnn: nnnn x 32 us => [0us..480us] default: t = 5*32us = 160us elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 64 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 table 6.2.6.2-5: register ch1_cfg4 (0x06) channel 1 configuration register 4 msb lsb content - - - - - en_e r_ch k t4_c rc ts4_flen[4:0] t4_len[3:0] reset value 0 0 0 0 0 0 0 00000 0000 access r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description en_er_chk : enable parity/crc check functionality 0b0: disable functionality 0b1: enable functionality t4_crc : psi5 frame error detection mode of frames starti ng in timeslot 4 0b0: psi5 sensor in parity mode 0b1: psi5 sensor in crc mode ts4_flen[4:0] : psi5 frame length of frames starting in timeslot 4 frame length includes start bit + data + parity/crc [tsx_flen] 16 = [frame length] 10 - [10] 10 0x0 = bit length of zero (=no frame) 0x01 - 0x17: frame length => [11..33] 0x18-0x1f:reserved default: = 0 t4_len[3:0] : timeslot 4 length 0b_nnnn: nnnn x 32 us => [0us..480us] default: t = 0*32us = 0us table 6.2.6.2-6: register ch1_cfg5 (0x07) channel 1 configuration register 5 msb lsb content - - - - - en_e r_ch k t5_c rc ts5_flen[4:0] t5_len[3:0] reset value 0 0 0 0 0 0 0 00000 0000 access r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description en_er_chk : enable parity/crc check functionality 0b0: disable functionality 0b1: enable functionality t5_crc : psi5 frame error detection mode of frames starti ng in timeslot 5 0b0: psi5 sensor in parity mode 0b1: psi5 sensor in crc mode ts5_flen[4:0] : psi5 frame length of frames starting in timeslot 5 frame length includes start bit + data + parity/crc [tsx_flen] 16 = [frame length] 10 - [10] 10 0x0 = bit length of zero (=no frame) 0x01 - 0x17: frame length => [11..33] 0x18 - 0x1f: reserved default: = 0 t5_len[3:0] : timeslot 5 length 0b_nnnn: nnnn x 32 us => [0us..480us] default: t = 0*32us = 0us elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 65 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 table 6.2.6.2-7: register ch1_cfg6 (0x08) channel 1 configuration register 6 msb lsb content - - - - - en_e r_ch k t6_c rc ts6_flen[4:0] t6_len[3:0] reset value 0 0 0 0 0 0 0 00000 0000 access r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description en_er_chk : enable parity/crc check functionality 0b0: disable functionality 0b1: enable functionality t6_crc : psi5 frame error detection mode of frames starti ng in timeslot 6 0b0: psi5 sensor in parity mode 0b1: psi5 sensor in crc mode ts6_flen[4:0] : psi5 frame length of frames starting in timeslot 6 frame length includes start bit + data + parity/crc [tsx_flen] 16 = [frame length] 10 - [10] 10 0x0 = bit length of zero (=no frame) 0x01 - 0x17: frame length => [11..33] 0x18-0x1f:reserved default:= 0 t6_len[3:0] : timeslot 6 length 0b_nnnn: nnnn x 32 us => [0us..480us] default: t = 0*32us = 0us table 6.2.6.2-8: register ch1_cfg7 (0x09) channel 1 configuration register 7 msb lsb content - - - - spi_buf- fer_cnfg[1 :0] sync_dly[9:0] reset value 0 0 0 0 11 0000 access r/w r/w r/w r/w r/w r/w bit description spi_buffer_cnfg[1:0] : spi buffer (=96bit) configuration 0b00: 48bit/buffer;2 partial buffers; buffer identi fiers[0,1] 0b01: 32bit/buffer;3 partial buffers; buffer identi fiers[0,1,2] 0b10: 24bit/buffer;4 partial buffers; buffer identi fiers[0,1,2,3] 0b11: 16bit/buffer;6 partial buffers; buffer identi fiers[0,1,2,3,4,5](=default) sync_dly[9:0] : sync pulse delay 0xnnn: nnn x 8/fclk_int =>[0us..682us] table 6.2.6.2-9: register ch2_cfg1 (0x0a) channel 2 configuration register 1 msb lsb content idac_ cnt_ mode idac_cnt_i nc2[1:0] idac_cnt_i nc1[1:0] en_e r_ch k t1_c rc ts1_flen[4:0] t1_len[3:0] reset value 0 00 00 0 0 00011 0100 access r/w r/w r/w r/w r/w r/w r/w bit description idac_cnt_mode : reserved idac_cnt_inc2[1:0] : reserved idac_cnt_inc1[1:0] : reserved en_er_chk : see ch1_cfg1 t1_crc : see ch1_cfg1 ts1_flen[4:0] : see ch1_cfg1 t1_len[3:0] : see ch1_cfg1 elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 66 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 table 6.2.6.2-10: register ch2_cfg2 (0x0b) channel 2 configuration register 2 msb lsb content - idac_cnt_d ec2[1:0] idac_cnt_d ec1[1:0] en_e r_ch k t2_c rc ts2_flen[4:0] t2_len[3:0] reset value 0 01 01 0 0 00011 0101 access r/w r/w r/w r/w r/w r/w r/w bit description idac_cnt_dec2[1:0] : reserved idac_cnt_dec1[1:0] : reseved en_er_chk : see ch1_cfg2 t2_crc : see ch1_cfg2 ts2_flen[4:0] : see ch1_cfg2 t2_len[3:0] : see ch1_cfg2 table 6.2.6.2-11: register ch2_cfg3 (0x0c) channel 2 configuration register 3 msb lsb content - - - - - en_e r_ch k t3_c rc ts3_flen[4:0] t3_len[3:0] reset value 0 0 0 0 0 0 0 00011 0101 access r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description en_er_chk : see ch1_cfg3 t3_crc : see ch1_cfg3 ts3_flen[4:0] : see ch1_cfg3 t3_len[3:0] : see ch1_cfg3 table 6.2.6.2-12: register ch2_cfg4 (0x0d) channel 2 configuration register 4 msb lsb content - - - - - en_e r_ch k t4_c rc ts4_flen[4:0] t4_len[3:0] reset value 0 0 0 0 0 0 0 00000 0000 access r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description en_er_chk : see ch1_cfg4 t4_crc : see ch1_cfg4 ts4_flen[4:0] : see ch1_cfg4 t4_len[3:0] : see ch1_cfg4 table 6.2.6.2-13: register ch2_cfg5 (0x0e) channel 2 configuration register 5 msb lsb content - - - - - en_e r_ch k t5_c rc ts5_flen[4:0] t5_len[3:0] reset value 0 0 0 0 0 0 0 00000 0000 access r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description en_er_chk : see ch1_cfg5 t5_crc : see ch1_cfg5 ts5_flen[4:0] : see ch1_cfg5 t5_len[3:0] : see ch1_cfg5 elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 67 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 table 6.2.6.2-14: register ch2_cfg6 (0x0f) channel 2 configuration register 6 msb lsb content - - - - - en_e r_ch k t6_c rc ts6_flen[4:0] t6_len[3:0] reset value 0 0 0 0 0 0 0 00000 0000 access r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description en_er_chk : see ch1_cfg6 t6_crc : see ch1_cfg6 ts6_flen[4:0] : see ch1_cfg6 t6_len[3:0] : see ch1_cfg6 table 6.2.6.2-15: register ch2_cfg7 (0x10) channel 2 configuration register 7 msb lsb content - - - - spi_buf- fer_cnfg[1 :0] sync_dly[9:0] reset value 0 0 0 0 11 0000 access r/w r/w r/w r/w r/w r/w bit description spi_buffer_cnfg[1:0] : see ch1_cfg7 sync_dly[9:0] : see ch1_cfg7 table 6.2.6.2-16: register ch3_cfg1 (0x11) channel 3 configuration register 1 msb lsb content idac_ cnt_ mode idac_cnt_i nc2[1:0] idac_cnt_i nc1[1:0] en_e r_ch k t1_c rc ts1_flen[4:0] t1_len[3:0] reset value 0 00 00 0 0 00011 0100 access r/w r/w r/w r/w r/w r/w r/w bit description idac_cnt_mode : reserved idac_cnt_inc2[1:0] : reserved idac_cnt_inc1[1:0] : reserved en_er_chk : see ch1_cfg1 t1_crc : see ch1_cfg1 ts1_flen[4:0] : see ch1_cfg1 t1_len[3:0] : see ch1_cfg1 table 6.2.6.2-17: register ch3_cfg2 (0x12) channel 3 configuration register 2 msb lsb content - idac_cnt_d ec2[1:0] idac_cnt_d ec1[1:0] en_e r_ch k t2_c rc ts2_flen[4:0] t2_len[3:0] reset value 0 01 01 0 0 00011 0101 access r/w r/w r/w r/w r/w r/w r/w bit description idac_cnt_dec2[1:0] : reserved idac_cnt_dec1[1:0] : reserved en_er_chk : see ch1_cfg2 t2_crc : see ch1_cfg2 ts2_flen[4:0] : see ch1_cfg2 t2_len[3:0] : see ch1_cfg2 elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 68 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 table 6.2.6.2-18: register ch3_cfg3 (0x13) channel 3 configuration register 3 msb lsb content - - - - - en_e r_ch k t3_c rc ts3_flen[4:0] t3_len[3:0] reset value 0 0 0 0 0 0 0 00011 0101 access r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description en_er_chk : see ch1_cfg3 t3_crc : see ch1_cfg3 ts3_flen[4:0] : see ch1_cfg3 t3_len[3:0] : see ch1_cfg3 table 6.2.6.2-19: register ch3_cfg4 (0x14) channel 3 configuration register 4 msb lsb content - - - - - en_e r_ch k t4_c rc ts4_flen[4:0] t4_len[3:0] reset value 0 0 0 0 0 0 0 00000 0000 access r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description en_er_chk : see ch1_cfg4 t4_crc : see ch1_cfg4 ts4_flen[4:0] : see ch1_cfg4 t4_len[3:0] : see ch1_cfg4 table 6.2.6.2-20: register ch3_cfg5 (0x15) channel 3 configuration register 5 msb lsb content - - - - - en_e r_ch k t5_c rc ts5_flen[4:0] t5_len[3:0] reset value 0 0 0 0 0 0 0 00000 0000 access r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description en_er_chk : see ch1_cfg5 t5_crc : see ch1_cfg5 ts5_flen[4:0] : see ch1_cfg5 t5_len[3:0] : see ch1_cfg5 table 6.2.6.2-21: register ch3_cfg6 (0x16) channel 3 configuration register 6 msb lsb content - - - - - en_e r_ch k t6_c rc ts6_flen[4:0] t6_len[3:0] reset value 0 0 0 0 0 0 0 00000 0000 access r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description en_er_chk : see ch1_cfg6 t6_crc : see ch1_cfg6 ts6_flen[4:0] : see ch1_cfg6 t6_len[3:0] : see ch1_cfg6 elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 69 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 table 6.2.6.2-22: register ch3_cfg7 (0x17) channel 3 configuration register 7 msb lsb content - - - - spi_buf- fer_cnfg[1 :0] sync_dly[9:0] reset value 0 0 0 0 11 0000 access r/w r/w r/w r/w r/w r/w bit description spi_buffer_cnfg[1:0] : see ch3_cfg7 sync_dly[9:0] : see ch3_cfg7 table 6.2.6.2-23: register ch4_cfg1 (0x18) channel 4 configuration register 1 msb lsb content idac_ cnt_ mode idac_cnt_i nc2[1:0] idac_cnt_i nc1[1:0] en_e r_ch k t1_c rc ts1_flen[4:0] t1_len[3:0] reset value 0 00 00 0 0 00011 0100 access r/w r/w r/w r/w r/w r/w r/w bit description idac_cnt_mode : reserved idac_cnt_inc2[1:0] : reserved idac_cnt_inc1[1:0] : reserved en_er_chk : see ch1_cfg1 t1_crc : see ch1_cfg1 ts1_flen[4:0] : see ch1_cfg1 t1_len[3:0] : see ch1_cfg1 table 6.2.6.2-24: register ch4_cfg2 (0x19) channel 4 configuration register 2 msb lsb content - idac_cnt_d ec2[1:0] idac_cnt_d ec1[1:0] en_e r_ch k t2_c rc ts2_flen[4:0] t2_len[3:0] reset value 0 01 01 0 0 00011 0101 access r/w r/w r/w r/w r/w r/w r/w bit description idac_cnt_dec2[1:0] : reserved idac_cnt_dec1[1:0] : reserved en_er_chk : see ch1_cfg2 t2_crc : see ch1_cfg2 ts2_flen[4:0] : see ch1_cfg2 t2_len[3:0] : see ch1_cfg2 table 6.2.6.2-25: register ch4_cfg3 (0x1a) channel 4 configuration register 3 msb lsb content - - - - - en_e r_ch k t3_c rc ts3_flen[4:0] t3_len[3:0] reset value 0 0 0 0 0 0 0 00011 0101 access r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description en_er_chk : see ch1_cfg3 t3_crc : see ch1_cfg3 ts3_flen[4:0] : see ch1_cfg3 t3_len[3:0] : see ch1_cfg3 elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 70 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 table 6.2.6.2-26: register ch4_cfg4 (0x1b) channel 4 configuration register 4 msb lsb content - - - - - en_e r_ch k t4_c rc ts4_flen[4:0] t4_len[3:0] reset value 0 0 0 0 0 0 0 00000 0000 access r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description en_er_chk : see ch1_cfg4 t4_crc : see ch1_cfg4 ts4_flen[4:0] : see ch1_cfg4 t4_len[3:0] : see ch1_cgf4 table 6.2.6.2-27: register ch4_cfg5 (0x1c) channel 4 configuration register 5 msb lsb content - - - - - en_e r_ch k t5_c rc ts5_flen[4:0] t5_len[3:0] reset value 0 0 0 0 0 0 0 00000 0000 access r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description en_er_chk : see ch1_cfg5 t5_crc : see ch1_cfg5 ts5_flen[4:0] : see ch1_cfg5 t5_len[3:0] : see ch1_cfg5 table 6.2.6.2-28: register ch4_cfg6 (0x1d) channel 4 configuration register 6 msb lsb content - - - - - en_e r_ch k t6_c rc ts6_flen[4:0] t6_len[3:0] reset value 0 0 0 0 0 0 0 00000 0000 access r/w r/w r/w r/w r/w r/w r/w r/w r/w bit description en_er_chk : see ch1_cfg6 t6_crc : see ch1_cfg6 ts6_flen[4:0] : see ch1_cfg6 t6_len[3:0] : see ch1_cfg6 table 6.2.6.2-29: register ch4_cfg7 (0x1e) channel 4 configuration register 7 msb lsb content - - - - spi_buf- fer_cnfg[1 :0] sync_dly[9:0] reset value 0 0 0 0 11 0000 access r/w r/w r/w r/w r/w r/w bit description spi_buffer_cnfg[1:0] : see ch1_cgf7 sync_dly[9:0] : see ch1_cgf7 elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 71 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 6.2.6.2.1 timeslot length the timeslotx length (bit tx_len) is used to assign the frame identifier (fid) to received psi5 frames . tx_len is implemented as a counter. once loaded, it 's counting down to 0. t1_len is loaded with start of sync pulse (after sy nc_dly has expired). if t1_len has expired, the fol lowing counter t2_len is loaded ... until t6_len has expir ed. for tsx_len=0x00(=no frame) the tx_len counter is a lso loaded with 0 and expires with the next 2 s cloc k cycle. the timeslot length (bit tx_len) is used to assign the frame identifier (fid) to decoded psi5 frames. following two examples based on psi5-p10p-500/3l (airbag), show t he correlation of fid to tx_len counter. the fid is added to the psi5 sensor data by the manchester decoder ( md) once the first start bit (rising slope) is dete cted. example 1, default configuration; t3_len expires wi thin frame3. figure 6.2.6.2.1-1: example1: txlen configuration example 2 default configuration;t3_len expires afte r frame3;md_unex_fr_chx_fx is possible: note that unexpected frame errors md_unex_fr_chx_f[ 4...6] are flagged if 2 valid start bits are decoded with 2 nd start bit occures in t[4...6]_len (error condition , either frame too late, unexpected frame or tx_len configured wrong). figure 6.2.6.2.1-2: example2: txlen configuration elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 72 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 for active tx_len counter any sync pulse trigger is masked to prevent an abort of tx_len counter. this allows a faster ecu-2-sensor communication w/o change of reg ister configuration. the time slot ends with the last edge of the data p rotocol. note: decoded manchester data will be discarded for a sync pulse trigger during active tx_len counter to avoid storage / upload of corrupted data to uc. error wil l be flagged in error_status_x[sync_data_inv_ch1]. with next regular sync trigger - after tx_len count er is again in idle state - sensor data is stored / uploaded to uc. idle t 0 frame1 sync no reset of fid due to unexpected sync pulse 0b001 fid 0b000 frame2 0b010 flag sync_data_inv_chx = '1' 0b011 '1' - > discard decoded mcd data target: no storage / upload of data to c with wron g fid clear on read extention possible until mdc in idle state unexp. sync figure 6.2.6.2.1-3: example2: txlen configuration: unexptected sync pulse elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 73 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 6.2.6.3 error registers there are ten error status registers available for reading, which are cleared on read (clear on read, rc). the following error information is available: ? md unexpected frame for each frame and channel ? md no frames for each frame and channel ? md frame error for each frame and channel ? md parity error for each frame and channel ? reverse current status of each channel ? buffer configuration error of each channel ? diagnosis status of each channel ? over current status of each channel ? uart/spi status information (invalid address, inval id command, spi clock erreor, uart read request col lision) details are described in the following register tab le. table 6.2.6.3-1: error status register register name address description error_status_1 0x25 global asic errors error_status_2 0x26 channel errors error_status_3 0x27 four error bits per frame (1-4) c hannel 1 error_status_4 0x28 four error bits per frame (5-6) c hannel 1 and analog errors error_status_5 0x29 four error bits per frame (1-4)ch annel 2 error_status_6 0x2a four error bits per frame (5-6)ch annel 2 and analog errors error_status_7 0x2b four error bits per frame (1-4)ch annel 3 error_status_8 0x2c four error bits per frame (5-6)ch annel 3 and analog errors error_status_9 0x2d four error bits per frame (1-4)ch annel 4 error_status_10 0x2e four error bits per frame (5-6)c hannel 4 and analog errors reading of unused bits will always return '0' and w riting of unused bits don't care. writing to read o nly or read on clear registers don't care. the spi echo response t o a write request is independently of register type (r/w, r, rc). elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 74 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 table 6.2.6.3-2: register error_status_1 (0x25) global asic errors msb lsb content - - - - - - - - uart _spi_i nv_a ddre ss vbus _ov diag_ ot spi_c lk_e rr uart _spi_ col- li- sion uart _spi_i nv_c md uart _fer r uart _per r reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 access r/c r/c r/c1 r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/ c r/c bit description uart_spi_inv_address : uart/spi address check 0b0: valid address 0b1: invalid address vbus_ov : vbus over voltage bit 0b0: no over voltage; signal vbus_ov_f = 0 0b1: over voltage; signal vbus_ov_f = 1 diag_ot : overtemperatur bit 0b0: no overtemperature; signal i_ot = 0 0b1: overtemperature; signal i_ot = 1 spi_clk_err : spi clock error 0b0: no clock error 0b1: spi clock error (number of clock cycles 16) uart_spi_collision : uart/spi read request collision status latch (cl ear on read) 0b0: no collision happend 0b1: uart/spi read request received while last read was not completed yet uart_spi_inv_cmd : uart/spi command error status latch (clear on re ad) 0b0: no command error 0b1: invalid command uart_ferr : uart frame error status latch (clear on read) 0b0: no frame error seen 0b1: frame error detected uart_perr : uart parity error status latch (clear on read) 0b0: no parity error seen 0b1: parity error detected table 6.2.6.3-3: register error_status_2 (0x26) channel errors msb lsb content - - - - - - - - - - - - ch_e rr_4 ch_e rr_3 ch_e rr_2 ch_e rr_1 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 access r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c bit description ch_err_4 : channel 4 error status (overall) 0b000: all bits of error_status_3 + error_status_4 are equal to '0' (= or combination of these bits) 0b001: number of bits with '1' of error_status_3 + error_status_4 is higher or equal to 1 (= or combin ation of these bits) ch_err_3 : channel 3 error status (overall) 0b000: all bits of error_status_7 + error_status_8 are equal to '0' (= or combination of these bits) 0b001: number of bits with '1' of error_status_7 + error_status_8 is higher or equal to 1 (= or combin ation of these bits) ch_err_2 : channel 2 error status (overall) 0b000: all bits of error_status_5 + error_status_6 are equal to '0' (= or combination of these bits) 0b001: number of bits with '1' of error_status_5 + error_status_6 is higher or equal to 1 (= or combin ation of these bits) ch_err_1 : channel 1 error status (overall) 0b000: all bits of error_status_3 + error_status_4 are equal to '0' (= or combination of these bits) 0b001: number of bits with '1' of error_status_3 + error_status_4 is higher or equal to 1 (= or combin ation of these bits) elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 75 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 table 6.2.6.3-4: register error_status_3 (0x27) four error bits per frame (1-4) channel 1 msb lsb content md_u nex_ fr_c h1_f4 md_n o_fr _ch1 _f4 md_f err_ fr_c h1_f4 md_p err_ fr_c h1_f4 md_u nex_ fr_c h1_f3 md_n o_fr _ch1 _f3 md_f err_ fr_c h1_f3 md_p err_ fr_c h1_f3 md_u nex_ fr_c h1_f2 md_n o_fr _ch1 _f2 md_f err_ fr_c h1_f2 md_p err_ fr_c h1_f2 md_u nex_ fr_c h1_f1 md_n o_fr _ch1 _f1 md_f err_ fr_c h1_f1 md_p err_ fr_c h1_f1 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 access r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c bit description md_unex_fr_ch1_f4 : manchester decoder unexpected frame received 0b0: no unexpected frame received 0b1: unexpected frame received md_no_fr_ch1_f4 : manchester decoder no frame received (clear on r ead) 0b0: frame received (in expected time slot) 0b1: no frame received (in expected time slot) md_ferr_fr_ch1_f4 : manchester decoder frame error status latch (cle ar on read) 0b0: no frame error seen 0b1: frame error detected md_perr_fr_ch1_f4 : manchester decoder parity/crc error status latch (clear on read) 0b0: no parity/crc error seen 0b1: parity/crc error detected md_unex_fr_ch1_f3 : see md_unex_fr_ch1_f4 md_no_fr_ch1_f3 : see md_no_fr_ch1_f4 md_ferr_fr_ch1_f3 : see md_ferr_fr_ch1_f4 md_perr_fr_ch1_f3 : see md_perr_fr_ch1_f4 md_unex_fr_ch1_f2 : see md_unex_fr_ch1_f4 md_no_fr_ch1_f2 : see md_no_fr_ch1_f4 md_ferr_fr_ch1_f2 : see md_ferr_fr_ch1_f4 md_perr_fr_ch1_f2 : see md_perr_fr_ch1_f4 md_unex_fr_ch1_f1 : see md_unex_fr_ch1_f4 md_no_fr_ch1_f1 : see md_no_fr_ch1_f4 md_ferr_fr_ch1_f1 : see md_ferr_fr_ch1_f4 md_perr_fr_ch1_f1 : see md_perr_fr_ch1_f4 elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 76 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 table 6.2.6.3-5: register error_status_4 (0x28) four error bits per frame (5-6) channel 1 a nd analog errors msb lsb content - - sync _dat a_ inv_c h1 rev_ cur_ ch1 buff _err _ch1 oc_c h1 diag_ch1[1: 0] md_u nex_ fr_c h1_f6 md_n o_fr _ch1 _f6 md_f err_ fr_c h1_f6 md_p err_ fr_c h1_f6 md_u nex_ fr_c h1_f5 md_n o_fr _ch1 _f5 md_f err_ fr_c h1_f5 md_p err_ fr_c h1_f5 reset value 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 access r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c bit description sync_data_ inv_ch1 : reverse current status of channel 1 0b0: no sync pulse trigger during active tx_len cou nter 0b1: sync pulse trigger during active tx_len counte r occurred rev_cur_ch1 : reverse current status of channel 1 0b0: no reverse current detected 0b1: reverse current detected buff_err_ch1 : data buffer (96bit) configuration error 0b0: no configuration error 0b1: configuration error oc_ch1 : channel 1 over current status 0b0: no over current 0b1: over current diag_ch1[1:0] : channel 1 diagnosis status code (clear on read) 0b00: no error 0b01 leakage to gnd 0b10: leakage to vbat (soft short) / open load md_unex_fr_ch1_f6 : see md_unex_fr_ch1_f4 md_no_fr_ch1_f6 : see md_no_fr_ch1_f4 md_ferr_fr_ch1_f6 : see md_ferr_fr_ch1_f4 md_perr_fr_ch1_f6 : see md_perr_fr_ch1_f4 md_unex_fr_ch1_f5 : see md_unex_fr_ch1_f4 md_no_fr_ch1_f5 : see md_no_fr_ch1_f4 md_ferr_fr_ch1_f5 : see md_ferr_fr_ch1_f4 md_perr_fr_ch1_f5 : see md_perr_fr_ch1_f4 table 6.2.6.3-6: register error_status_5 (0x29) four error bits per frame (1-4)channel 2 msb lsb content md_u nex_ fr_c h2_f4 md_n o_fr _ch2 _f4 md_f err_ fr_c h2_f4 md_p err_ fr_c h2_f4 md_u nex_ fr_c h2_f3 md_n o_fr _ch2 _f3 md_f err_ fr_c h2_f3 md_p err_ fr_c h2_f3 md_u nex_ fr_c h2_f2 md_n o_fr _ch2 _f2 md_f err_ fr_c h2_f2 md_p err_ fr_c h2_f2 md_u nex_ fr_c h2_f1 md_n o_fr _ch2 _f1 md_f err_ fr_c h2_f1 md_p err_ fr_c h2_f1 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 access r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c bit description md_unex_fr_ch2_f4 : see md_unex_fr_ch1_f4 md_no_fr_ch2_f4 : see md_no_fr_ch1_f4 md_ferr_fr_ch2_f4 : see md_ferr_fr_ch1_f4 md_perr_fr_ch2_f4 : see md_perr_fr_ch1_f4 md_unex_fr_ch2_f3 : see md_unex_fr_ch1_f4 md_no_fr_ch2_f3 : see md_no_fr_ch1_f4 md_ferr_fr_ch2_f3 : see md_ferr_fr_ch1_f4 md_perr_fr_ch2_f3 : see md_perr_fr_ch1_f4 md_unex_fr_ch2_f2 : see md_unex_fr_ch1_f4 md_no_fr_ch2_f2 : see md_no_fr_ch1_f4 md_ferr_fr_ch2_f2 : see md_ferr_fr_ch1_f4 md_perr_fr_ch2_f2 : see md_perr_fr_ch1_f4 md_unex_fr_ch2_f1 : see md_unex_fr_ch1_f4 md_no_fr_ch2_f1 : see md_no_fr_ch1_f4 md_ferr_fr_ch2_f1 : see md_ferr_fr_ch1_f4 md_perr_fr_ch2_f1 : see md_perr_fr_ch1_f4 elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 77 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 table 6.2.6.3-7: register error_status_6 (0x2a) four error bits per frame (5-6)channel 2 an d analog errors msb lsb content - - sync _dat a_ inv_c h2 rev_ cur_ ch2 buf- fer_ err_ ch2 oc_c h2 diag_ch2[1: 0] md_u nex_ fr_c h2_f6 md_n o_fr _ch2 _f6 md_f err_ fr_c h2_f6 md_p err_ fr_c h2_f5 md_u nex_ fr_c h2_f5 md_n o_fr _ch2 _f5 md_f err_ fr_c h2_f5 md_p err_ fr_c h2_f5 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 access r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c bit description sync_data_ inv_ch2 : reverse current status of channel 2 0b0: no sync pulse trigger during active tx_len cou nter 0b1: sync pulse trigger during active tx_len counte r occurred rev_cur_ch2 : reverse current status of channel 2 0b0: no reverse current detected 0b1: reverse current detected buffer_err_ch2 : data buffer (96bit) configuration error 0b0: no configuration error 0b1: configuration error oc_ch2 : channel 2 over current status 0b0: no over current 0b1: over current diag_ch2[1:0] : channel 1 diagnosis status code (clear on read) 0b00: no error 0b01 leakage to gnd 0b10: leakage to vbat (soft short) / open load md_unex_fr_ch2_f6 : see md_unex_fr_ch1_f4 md_no_fr_ch2_f6 : see md_no_fr_ch1_f4 md_ferr_fr_ch2_f6 : see md_ferr_fr_ch1_f4 md_perr_fr_ch2_f5 : see md_perr_fr_ch1_f4 md_unex_fr_ch2_f5 : see md_unex_fr_ch1_f4 md_no_fr_ch2_f5 : see md_no_fr_ch1_f4 md_ferr_fr_ch2_f5 : see md_ferr_fr_ch1_f4 md_perr_fr_ch2_f5 : see md_perr_fr_ch1_f4 table 6.2.6.3-8: register error_status_7 (0x2b) four error bits per frame (1-4)channel 3 msb lsb content md_u nex_ fr_c h3_f4 md_n o_fr _ch3 _f4 md_f err_ fr_c h3_f4 md_p err_ fr_c h3_f4 md_u nex_ fr_c h3_f3 md_n o_fr _ch3 _f3 md_f err_ fr_c h3_f3 md_p err_ fr_c h3_f3 md_u nex_ fr_c h3_f2 md_n o_fr _ch3 _f2 md_f err_ fr_c h3_f2 md_p err_ fr_c h3_f2 md_u nex_ fr_c h3_f1 md_n o_fr _ch3 _f1 md_f err_ fr_c h3_f1 md_p err_ fr_c h3_f1 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 access r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c bit description md_unex_fr_ch3_f4 : see md_unex_fr_ch1_f4 md_no_fr_ch3_f4 : see md_no_fr_ch1_f4 md_ferr_fr_ch3_f4 : see md_ferr_fr_ch1_f4 md_perr_fr_ch3_f4 : see md_perr_fr_ch1_f4 md_unex_fr_ch3_f3 : see md_unex_fr_ch1_f4 md_no_fr_ch3_f3 : see md_no_fr_ch1_f4 md_ferr_fr_ch3_f3 : see md_ferr_fr_ch1_f4 md_perr_fr_ch3_f3 : see md_perr_fr_ch1_f4 md_unex_fr_ch3_f2 : see md_unex_fr_ch1_f4 md_no_fr_ch3_f2 : see md_no_fr_ch1_f4 md_ferr_fr_ch3_f2 : see md_ferr_fr_ch1_f4 md_perr_fr_ch3_f2 : see md_perr_fr_ch1_f4 md_unex_fr_ch3_f1 : see md_unex_fr_ch1_f4 md_no_fr_ch3_f1 : see md_no_fr_ch1_f4 md_ferr_fr_ch3_f1 : see md_ferr_fr_ch1_f4 md_perr_fr_ch3_f1 : see md_perr_fr_ch1_f4 elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 78 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 table 6.2.6.3-9: register error_status_8 (0x2c) four error bits per frame (5-6)channel 3 an d analog errors msb lsb content - - sync _dat a_ inv_c h3 rev_ cur_ ch3 buff _err _ch3 oc_c h3 diag_ch3[1: 0] md_u nex_ fr_c h3_f6 md_n o_fr _ch3 _f6 md_f err_ fr_c h3_f6 md_p err_ fr_c h3_f6 md_u nex_ fr_c h3_f5 md_n o_fr _ch3 _f5 md_f err_ fr_c h3_f5 md_p err_ fr_c h3_f5 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 access r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c bit description sync_data_ inv_ch3 : reverse current status of channel 3 0b0: no sync pulse trigger during active tx_len cou nter 0b1: sync pulse trigger during active tx_len counte r occurred rev_cur_ch3 : reverse current status of channel 3 0b0: no reverse current detected 0b1: reverse current detected buff_err_ch3 : data buffer (96bit) configuration error 0b0: no configuration error 0b1: configuration error oc_ch3 : channel 3 over current status 0b0: no over current 0b1: over current diag_ch3[1:0] : channel 3 diagnosis status code (clear on read) 0b00: no error 0b01 leakage to gnd 0b10: leakage to vbat (soft short) / open load md_unex_fr_ch3_f6 : see md_unex_fr_ch1_f4 md_no_fr_ch3_f6 : see md_no_fr_ch1_f4 md_ferr_fr_ch3_f6 : see md_ferr_fr_ch1_f4 md_perr_fr_ch3_f6 : see md_perr_fr_ch1_f4 md_unex_fr_ch3_f5 : see md_unex_fr_ch1_f4 md_no_fr_ch3_f5 : see md_no_fr_ch1_f4 md_ferr_fr_ch3_f5 : see md_ferr_fr_ch1_f4 md_perr_fr_ch3_f5 : see md_perr_fr_ch1_f4 table 6.2.6.3-10: register error_status_9 (0x2d) four error bits per frame (1-4)channel 4 msb lsb content md_u nex_ fr_c h4_f4 md_n o_fr _ch4 _f4 md_f err_ fr_c h4_f4 md_p err_ fr_c h4_f4 md_u nex_ fr_c h4_f3 md_n o_fr _ch4 _f3 md_f err_ fr_c h4_f3 md_p err_ fr_c h4_f3 md_u nex_ fr_c h4_f2 md_n o_fr _ch4 _f2 md_f err_ fr_c h4_f2 md_p err_ fr_c h4_f2 md_u nex_ fr_c h4_f1 md_n o_fr _ch4 _f1 md_f err_ fr_c h4_f1 - md_p err_ fr_c h4_f1 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 access bit description md_unex_fr_ch4_f4 : see md_unex_fr_ch1_f4 md_no_fr_ch4_f4 : see md_no_fr_ch1_f4 md_ferr_fr_ch4_f4 : see md_ferr_fr_ch1_f4 md_perr_fr_ch4_f4 : see md_perr_fr_ch1_f4 md_unex_fr_ch4_f3 : see md_unex_fr_ch1_f4 md_no_fr_ch4_f3 : see md_no_fr_ch1_f4 md_ferr_fr_ch4_f3 : see md_ferr_fr_ch1_f4 md_perr_fr_ch4_f3 : see md_perr_fr_ch1_f4 md_unex_fr_ch4_f2 : see md_unex_fr_ch1_f4 md_no_fr_ch4_f2 : see md_no_fr_ch1_f4 md_ferr_fr_ch4_f2 : see md_ferr_fr_ch1_f4 md_perr_fr_ch4_f2 : see md_perr_fr_ch1_f4 md_unex_fr_ch4_f1 : see md_unex_fr_ch1_f4 md_no_fr_ch4_f1 : see md_no_fr_ch1_f4 md_ferr_fr_ch4_f1 : see md_ferr_fr_ch1_f4 -md_perr_fr_ch4_f1 : see md_perr_fr_ch1_f4 elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 79 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 table 6.2.6.3-11: register error_status_10 (0x2e) four error bits per frame (5-6)channel 4 an d analog errors msb lsb content - - sync _dat a_ inv_c h4 rev_ cur_ ch4 buff _err _ch4 oc_c h4 diag_ch4[1: 0] md_u nex_ fr_c h4_f6 md_n o_fr _ch4 _f6 md_f err_ fr_c h4_f6 md_p err_ fr_c h4_f6 md_u nex_ fr_c h4_f5 md_n o_fr _ch4 _f5 md_f err_ fr_c h4_f5 md_p err_ fr_c h4_f5 reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 access r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c r/c bit description sync_data_ inv_ch4 : reverse current status of channel 4 0b0: no sync pulse trigger during active tx_len cou nter 0b1: sync pulse trigger during active tx_len counte r occurred rev_cur_ch4 : reverse current status of channel 4 0b0: no reverse current detected 0b1: reverse current detected buff_err_ch4 : data buffer (96bit) configuration error 0b0: no configuration error 0b1: configuration error oc_ch4 : channel 4 over current status 0b0: no over current 0b1: over current diag_ch4[1:0] : channel 4 diagnosis status code (clear on read) 0b00: no error 0b01 leakage to gnd 0b10: leakage to vbat (soft short) / open load md_unex_fr_ch4_f6 : see md_unex_fr_ch1_f4 md_no_fr_ch4_f6 : see md_no_fr_ch1_f4 md_ferr_fr_ch4_f6 : see md_ferr_fr_ch1_f4 md_perr_fr_ch4_f6 : see md_perr_fr_ch1_f4 md_unex_fr_ch4_f5 : see md_unex_fr_ch1_f4 md_no_fr_ch4_f5 : see md_no_fr_ch1_f4 md_ferr_fr_ch4_f5 : see md_ferr_fr_ch1_f4 md_perr_fr_ch4_f5 : see md_perr_fr_ch1_f4 elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 80 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 6.2.6.4 diagnosis registers there are 8 (read only, r) registers available for diagnosis purposes. following diagnosis informations are available: ? voltages vdd,vbus,vsync,vdd_int ? voltages sifx table 6.2.6.4-1: diagnosis register register name address description diagnosis_adc_1_2 0x2f adc data:vdd_int,vdd diagnosis_adc_3_4 0x30 adc data:vsif2,vsif1 diagnosis:_adc_5_6 0x31 adc data:vsif4,vsif3 diagnosis_adc_7_8 0x32 adc data:vsync,vbus diagnosis_adc_9_10 0x33 adc data:vcp_gate reading of unused bits will always return '0' and w riting of unused bits don't care. writing to read o nly or read on clear registers don't care. the spi echo response t o a write request is independently of register type (r/w, r, rc). table 6.2.6.4-2: register diagnosis_adc_1_2 (0x2f) adc data:vdd_int,vdd msb lsb content adc_data_2[7:0] adc_data_1[7:0] reset value 0 0 access r r bit description adc_data_2[7:0] : adc data voltage level vdd_int adc_data_1[7:0] : adc data voltage level vdd table 6.2.6.4-3: register diagnosis_adc_3_4 (0x30) adc data:vsif2,vsif1 msb lsb content adc_data_4[7:0] adc_data_3[7:0] reset value 0 0 access r r bit description adc_data_4[7:0] : adc data voltage level vsif2 adc_data_3[7:0] : adc data voltage level vsif1 table 6.2.6.4-4: register diagnosis:_adc_5_6 (0x31) adc data:vsif4,vsif3 msb lsb content adc_data_6[7:0] adc_data_5[7:0] reset value 0 0 access r r bit description adc_data_6[7:0] : adc data voltage level vsif4 adc_data_5[7:0] : adc data voltage level vsif3 elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 81 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 table 6.2.6.4-5: register diagnosis_adc_7_8 (0x32) adc data:vsync,vbus msb lsb content adc_data_8[7:0] adc_data_7[7:0] reset value 0 0 access r r bit description adc_data_8[7:0] : adc data voltage level vsync adc_data_7[7:0] : adc data voltage level vbus table 6.2.6.4-6: register diagnosis_adc_9_10 (0x33) adc data:vcp_gate msb lsb content - - - - - - - - adc_data_9[7:0] reset value 0 0 0 0 0 0 0 0 0 access r r r r r r r r r bit description adc_data_9[7:0] : adc data voltage level vcp_gate elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 82 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 7 package information 7.1 qfn20l5 all devices are available in a pb free, rohs compli ant qfn20l5 plastic package according to jedec mo-2 20 k, variant vhhc-2. the package is classified to moistu re sensitivity level 3 (msl 3) according to jedec j -std-020 with a soldering peak temperature of (260+5)c. description symbol mm inch min typ max min typ max package height a 0.80 0.90 1.00 0.031 0.035 0.039 stand off a1 0.00 0.02 0.05 0.000 0.00079 0.002 thickness of terminal leads, including lead finish a 3 -- 0.20 ref -- -- 0.0079 ref -- width of terminal leads b 0.25 0.30 0.35 0.010 0.012 0.014 package length / width d / e -- 5.00 bsc -- -- 0.197 bsc -- length / width of exposed pad d2 / e2 3.50 3.65 3.80 0. 138 0.144 0.150 lead pitch e -- 0.65 bsc -- -- 0.026 bsc -- length of terminal for soldering to substrate l 0.35 0 .40 0.45 0.014 0.016 0.018 step cut depth (incl. plating layer) scd 0.075 0.100 0. 125 0.003 0.004 0.005 step cut length (incl. plating layer) scl 0.025 0.050 0 .075 0.001 0.002 0.003 number of terminal positions n 20 20 note: the mm values are valid, the inch values contains rounding errors elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 83 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 7.2 soic20 all devices are available in a pb free, rohs compli ant soic20 plastic package according to jedec ms-01 3-e, variant ac. the package is classified to moisture s ensitivity level 3 (msl 3) according to jedec j-std -020 with a soldering peak temperature of (260+5)c. description symbol mm inch min typ max min typ max package height a -- -- 2.65 -- -- 0.104 stand off a1 0.10 -- 0.30 0.004 -- 0.012 package body thickness a2 2.05 -- -- 0.081 -- -- width of terminal leads, inclusive lead finish b 0.31 -- 0.51 0.012 -- 0.020 thickness of terminal leads, inclusive lead finish c 0.20 -- 0.33 0.008 -- 0.013 package length d 12.80 bsc 0.504 bsc package width e 10.30 bsc 0.406 bsc package body width e1 7.50 bsc 0.295 bsc lead pitch e 1.27 bsc 0.050 bsc length of terminal for soldering to substrate l 0.4 -- 1.27 0.016 -- 0.050 body chamfer (45) h 0.25 -- 0.75 0.010 -- 0.030 angle of lead mounting area phi [] 0 -- 8 0 -- 8 mold release angle phi1 [] 5 -- 15 5 -- 15 number of terminal positions n 20 20 note: the mm values are valid, the inch values contains rounding errors elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 84 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 warning ? life support applications policy elmos semiconductor ag is continually working to im prove the quality and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing elmos semiconductor ag produ cts, to observe standards of safety, and to avoid situations in whi ch malfunction or failure of an elmos semiconductor ag product could cause loss of human life, body injury or dama ge to property. in the development of your design, please ensure that elmos semiconductor ag products are use d within specified operating ranges as set forth in the most recent product specifications. general disclaimer information furnished by elmos semiconductor ag is believed to be accurate and reliable. however, no r esponsib- ility is assumed by elmos semiconductor ag for its use, nor for any infringements of patents or other rights of third parties, which may result from its use. no license is granted by implication or otherwise under any pa tent or patent rights of elmos semiconductor ag. elmos semiconduct or ag reserves the right to make changes to this do cument or the products contained therein without prior not ice, to improve performance, reliability, or manufa cturability. application disclaimer circuit diagrams may contain components not manufac tured by elmos semiconductor ag, which are included as means of illustrating typical applications. consequ ently, complete information sufficient for construc tion purposes is not necessarily given. the information in the appli cation examples has been carefully checked and is b elieved to be entirely reliable. however, no responsibility is as sumed for inaccuracies. furthermore, such informati on does not convey to the purchaser of the semiconductor device s described any license under the patent rights of elmos semiconductor ag or others. contact information headquarters elmos semiconductor ag heinrich-hertz-str. 1 ? d-44227 dortmund (germany) Y : +492317549100 : sales-germany@elmos.com : www.elmos.com sales and application support office north america elmos na. inc. 32255 northwestern highway ? suite 220 farmington h ills mi 48334 (usa) Y : +12488653200 : sales-usa@elmos.com sales and application support office china elmos semiconductor technology (shanghai) co., ltd. unit 16b, 16f zhao feng world trade building, no. 369 jiang su road, chang ning district, shanghai, pr china, 200050 Y : +86216210 0908 : sales-china@elmos.com sales and application support office korea elmos korea b-1007, u-space 2, #670 daewangpangyo-ro, sampyoung-dong, bunddang-gu, sungnam-si kyounggi-do 463-400 korea Y : +82317141131 : sales-korea@elmos.com sales and application support office japan elmos japan k.k. br shibaura n bldg. 7f 3-20-9 shibaura, minato-ku, tokyo 108-0023 japan Y : +81334517101 : sales-japan@elmos.com sales and application support office singapore elmos semiconductor singapore pte ltd. 3a international business park #09-13 icon@ibp ? 609935 singapore Y : +65 6908 1261 : sales-singapore@elmos.com ? elmos semiconductor ag, 2016. reproduction, in part or whole, without the prior written consent of elmos semiconductor ag, is prohi bited. elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 85 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 8 index table of content features........................................... ................................................... ................................................... ........................1 applications....................................... ................................................... ................................................... ......................1 general description................................ ................................................... ................................................... .................1 ordering information............................... ................................................... ................................................... .................1 typical application circuit........................ ................................................... ................................................... ...............1 functional diagram................................. ................................................... ................................................... .................2 1 package pinout qfn20l5,so20...................... ................................................... ................................................... ...3 1.1 pin description qfn20l5........................ ................................................... ................................................... .....4 1.2 pin description so20........................... ................................................... ................................................... ........5 2 application description.......................... ................................................... ................................................... ...............6 2.1 application circuits........................... ................................................... ................................................... ............6 2.1.1 application circuits......................... ................................................... ................................................... ......6 3 functional safety................................ ................................................... ................................................... ..................9 3.1 functional safety requirements................. ................................................... ................................................... .9 3.2 fmeda.......................................... ................................................... ................................................... ...............9 3.2.1 safety measures mandatory to reach asil level c................................................. .................................9 4 operating conditions............................. ................................................... ................................................... .............10 4.1 absolute maximum ratings....................... ................................................... ................................................... .10 4.2 recommended operating conditions............... ................................................... ............................................11 5 detailed electrical specification................ ................................................... ................................................... .........13 5.1 analog part.................................... ................................................... ................................................... ......13 5.1.1 supply....................................... ................................................... ................................................... ......13 5.1.1.1 ldo control block.......................... ................................................... ..............................................13 5.1.1.1.1 electrical parameter of ldo.............. ................................................... ...................................13 5.1.1.1.2 electrical parameter control voltage..... ................................................... ..............................15 5.1.1.2 charge pump for sync voltage............... ................................................... .....................................15 5.1.2 por and power-up sequence.................... ................................................... ................................15 5.1.3 psi5 interface............................... ................................................... ..................................................1 6 5.1.3.1 interface driver........................... ................................................... ................................................... 16 5.1.3.2 over current detection and limitation...... ................................................... ...................................17 5.1.3.3 reverse current detection and limitation... ................................................... .................................17 5.1.3.3.1 reverse current flow from sifx to vbus... ................................................... ........................17 5.1.3.3.2 reverse current flow from sifx to csync.. ................................................... ......................18 5.1.3.4 data comparator............................ ................................................... ...............................................18 5.1.3.5 sync pulse generation...................... ................................................... ...........................................18 5.1.3.5.1 sync pulse generation dc-parameter....... ................................................... ..........................18 5.1.3.5.2 sync pulse generation ac parameter....... ................................................... ..........................19 5.1.3.6 sync pulse generation by pin trig.......... ................................................... ..................................19 5.1.4 clock generation............................. ................................................... ............................................20 5.1.5 diagnosis.................................... ................................................... ................................................... ...21 5.1.5.1 adc voltage measurements................... ................................................... .....................................21 5.1.5.2 over temperature monitoring (ot)........... ................................................... ...................................21 5.1.5.3 vbus over voltage monitoring............... ................................................... .....................................22 5.2 digital part................................... ................................................... ................................................... ........23 5.2.1 spi.......................................... ................................................... ................................................... ............23 5.2.1.1 dc electrical parameter table of spi ios... ................................................... .................................23 5.2.1.2 ac electrical parameter table of spi i/os.. ................................................... .................................23 6 functional description .......................... ................................................... ................................................... .............24 6.1 analog part.................................... ................................................... ................................................... ......24 6.1.1 supply....................................... ................................................... ................................................... ......24 6.1.1.1 ldo control block.......................... ................................................... ..............................................24 6.1.1.2 charge pump for sync voltage............... ................................................... .....................................24 elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 86 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 6.1.2 por and power-up sequence.................... ................................................... ................................25 6.1.3 psi5 interface............................... ................................................... ..................................................2 5 6.1.3.1 interface driver........................... ................................................... ................................................... 25 6.1.3.2 over current detection and limitation...... ................................................... ...................................25 6.1.3.3 reverse current detection and limitation... ................................................... .................................25 6.1.3.3.1 reverse current flow from sifx to vbus... ................................................... ........................25 6.1.3.3.2 reverse current flow from sifx to csync.. ................................................... ......................26 6.1.3.4 quiescent current threshold tracking....... ................................................... ..................................26 6.1.3.5 data comparator............................ ................................................... ...............................................26 6.1.3.6 sync pulse generation...................... ................................................... ...........................................27 6.1.3.7 sync pulse generation by pin trig.......... ................................................... ..................................28 6.1.3.8 sync pulse generation by uart/spi command.. ................................................... .......................29 6.1.4 clock generation............................. ................................................... ............................................29 6.1.5 diagnosis.................................... ................................................... ................................................... ...30 6.1.5.1 adc voltage measurements................... ................................................... .....................................30 6.1.5.2 over temperature monitoring (ot)........... ................................................... ...................................30 6.1.5.3 vbus over voltage monitoring............... ................................................... .....................................31 6.1.5.4 leakage to gnd, leakage to vbat and open lo ad................................................. .....................31 6.1.5.5 gnd loss detection......................... ................................................... ............................................31 6.1.5.6 transfer of error- and diagnosis informatio n to controller.................................... ........................31 6.1.5.6.1 error information........................ ................................................... ...........................................31 6.2 digital part................................... ................................................... ................................................... ........35 6.2.1 communication interface to micro controller.. ................................................... ..........35 6.2.2 manchester decoder........................... ................................................... .......................................35 6.2.2.1 manchester data handling and buffer archite cture.............................................. ..........................35 6.2.2.1.1 uart data buffer......................... ................................................... .................................36 6.2.2.1.2 spi data buffer.......................... ................................................... ....................................36 6.2.2.2 manchester bit encoding.................... ................................................... ..........................................38 6.2.2.2.1 definition of data edge / compensation ed ge................................................. .........................38 6.2.2.2.2 interpretation with manchester decoder... ................................................... ............................38 6.2.2.2.3 definition of duty cycle................. ................................................... .......................................38 6.2.2.2.4 decoder error flags...................... ................................................... ........................................39 6.2.3 spi.......................................... ................................................... ................................................... ............39 6.2.3.1 error handling............................. ................................................... ..................................................4 1 6.2.3.2 overview of communication frames........... ................................................... .................................43 6.2.3.3 overview of spi commands................... ................................................... .......................................44 6.2.3.4 no operation command....................... ................................................... ........................................44 6.2.3.5 write configuration register command....... ................................................... ................................44 6.2.3.6 software reset command..................... ................................................... .......................................45 6.2.3.7 read configuration register command........ ................................................... ...............................45 6.2.3.8 sync pulse command......................... ................................................... .......................................45 6.2.3.9 read sensor data........................... ................................................... ..............................................46 6.2.3.9.1 read of 16bit (11bit sensor data)........ ................................................... .................................48 6.2.3.9.2 read of 24bit (19bit sensor data)........ ................................................... .................................49 6.2.3.9.3 read of 32bit (27bit sensor data)........ ................................................... .................................49 6.2.3.9.4 read of 48bit (43bit sensor data)........ ................................................... .................................49 6.2.4 uart......................................... ................................................... ................................................... .........50 6.2.4.1 error handling ............................ ................................................... ..................................................5 0 6.2.4.2 packet frame definition.................... ................................................... ............................................52 6.2.4.3 uart frame definition...................... ................................................... ...........................................52 6.2.4.4 overview of communication frames........... ................................................... .................................53 6.2.4.5 overview of uart commands.................. ................................................... ...................................53 6.2.4.6 write register command..................... ................................................... .........................................54 6.2.4.7 read register command...................... ................................................... .......................................54 6.2.4.8 short sync pulse command................... ................................................... ....................................55 elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 87 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 6.2.4.9 long sync pulse command.................... ................................................... ...................................55 6.2.4.10 no sync pulse command..................... ................................................... ....................................55 6.2.4.11 software reset command.................... ................................................... ......................................56 6.2.4.12 response to read register command......... ................................................... .............................56 6.2.4.13 transfer psi5 data........................ ................................................... .............................................57 6.2.5 xcrc[5:0] calculation........................ ................................................... ..................................................5 8 6.2.6 configuration................................ ................................................... ................................................59 6.2.6.1 asic configuration......................... ................................................... ..............................................59 6.2.6.1.1 asynchronous mode........................ ................................................... .....................................63 6.2.6.2 timeslot configuration..................... ................................................... .............................................63 6.2.6.2.1 timeslot length.......................... ................................................... ..........................................73 6.2.6.3 error registers............................ ................................................... ..................................................7 5 6.2.6.4 diagnosis registers........................ ................................................... ..............................................82 7 package information.............................. ................................................... ................................................... .............84 7.1 qfn20l5........................................ ................................................... ................................................... ............84 7.2 soic20......................................... ................................................... ................................................... ..............85 8 index............................................ ................................................... ................................................... .......................87 illustration index figure 2.1.1-1: application circuit with ldo....... ................................................... ................................................... ....6 figure 2.1.1-2: application circuit with vbus suppl ied from ecu....................................... ........................................7 figure 6.1.3.5-1: current modulation............... ................................................... ................................................... .....25 figure 6.1.3.6-1: sync pulse timing diagram........ ................................................... .................................................26 figure 6.1.3.7-1: long sync pulse trigger via pin t rig................................................ ..........................................27 figure 6.1.3.7-2: short sync pulse trigger via pin trig............................................... ..........................................27 figure 6.1.3.8-1: short sync ptrigger via uart..... ................................................... ...............................................28 figure 6.1.3.8-2: short sync pulse trigger via spi. ................................................... ..............................................28 figure 6.2.2.1-1: buffer architecture overview..... ................................................... ................................................... 34 figure 6.2.2.1.1-1: uart data buffer............... ................................................... ................................................... ....35 figure 6.2.2.1.2-1: spi data buffer................ ................................................... ................................................... .......36 figure 6.2.2.1.2-2: spi data buffer incl. 4 frames. ................................................... .................................................36 figure 6.2.2.2.3-1: example mcd duty cycle......... ................................................... ................................................37 figure 6.2.2.2.4-1: md_ferr_chx_f1................. ................................................... .................................................38 figure 6.2.2.2.4-2: set of error flags (2errors; da ta=0x3ff).......................................... ...........................................38 figure 6.2.3-1: data flow graphic.................. ................................................... ................................................... ......39 figure 6.2.3.1-1: spi error handling example 1..... ................................................... .................................................40 figure 6.2.3.1-2: spi error handling example 2..... ................................................... .................................................40 figure 6.2.3.1-3: spi error handling example 3..... ................................................... .................................................40 figure 6.2.3.1-4: spi error handling example 4..... ................................................... .................................................40 figure 6.2.3.4-1: spi nop command.................. ................................................... ................................................... .43 figure 6.2.3.5-1: spi write register command....... ................................................... ................................................44 figure 6.2.3.6-1: spi software reset command....... ................................................... ..............................................44 figure 6.2.3.7-1: spi read register command........ ................................................... ..............................................44 figure 6.2.3.8-1: spi sync pulse command........... ................................................... ...............................................45 figure 6.2.3.9-1: valid read sensor data window 1.. ................................................... ................................................46 figure 6.2.3.9-2: valid read sensor data window 2.. ................................................... ................................................46 figure 6.2.3.9.1-1: spi read sensor data 16bit..... ................................................... .................................................47 figure 6.2.3.9.1-2: spi read sensor data 16bit-requ est at sdi_rxd -1st spi frame-..................... ........................47 figure 6.2.3.9.1-3: response to spi read sensor dat a 16bit at sdo_txd -2nd spi frame-................. .................47 figure 6.2.3.9.2-1: read sensor data 24bit command. ................................................... ...........................................48 figure 6.2.3.9.3-1: read sensor data 32bit command. ................................................... ...........................................48 figure 6.2.3.9.4-1: read sensor data 48bit command. ................................................... ...........................................48 figure 6.2.4.1-1: uart error handling example 1.... ................................................... ..............................................49 figure 6.2.4.1-2: uart error handling example 2.... ................................................... ..............................................49 figure 6.2.4.1-3: syncpulse staggering............. ................................................... ................................................... ....50 elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 88 / 89 4 channel multi-mode psi5 transceiver e521.41 production data ? apr 27, 2016 figure 6.2.4.3-1: uart data transmission........... ................................................... ..................................................5 2 figure 6.2.4.6-1: write register command packet fra me................................................. ........................................53 figure 6.2.4.7-1: read register command packet fram e.................................................. .......................................53 figure 6.2.4.8-1: short sync command packet frame.. ................................................... .......................................54 figure 6.2.4.9-1: long sync command packet frame... ................................................... .......................................54 figure 6.2.4.10-1: no sync pulse command packet fra me................................................. ...................................55 figure 6.2.4.11-1: software reset command frame.... ................................................... ..........................................55 figure 6.2.4.12-1: response to read register comman d packet frame..................................... ............................56 figure 6.2.4.13-1: example: upload psi5 data minimu m packet frame..................................... ..............................56 figure 6.2.4.13-2: example: upload psi5 data maximu m packet frame..................................... .............................56 figure 6.2.5-1: xcrc-calculation for spi frames.... ................................................... ................................................57 figure 6.2.5-2: xcrc: example transfer psi5 data... ................................................... ............................................57 figure 6.2.5-3: xcrc: example response to read comm and................................................ .................................58 figure 6.2.5-4: xcrc example read sensor data 24bit ................................................... ........................................58 figure 6.2.6.2.1-1: example1: txlen configuration.. ................................................... .............................................72 figure 6.2.6.2.1-2: example2: txlen configuration.. ................................................... .............................................72 figure 6.2.6.2.1-3: example2: txlen configuration: unexptected sync pulse............................. ............................73 elmos semiconductor ag reserves the right to change the detail specifications as may be required to pe rmit improvements in the design of its products. elmos semiconductor ag data sheet qm-no.: 25ds0109e.06 89 / 89 |
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